Version 1 ColdFire Debug (CF1_DEBUG)
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
20-49
20.4.1.5.20
WRITE_MEM.sz, WRITE_MEM.sz_WS
Write data at the specified memory address. The reference address is transmitted as three 8-bit packets
(msb to lsb) immediately after the command packet. The access attributes are defined by BAAR[TT,TM].
The hardware forces low-order address bits to zeros for word and longword accesses to ensure these
accesses are on 0-modulo-size alignments. If the with-status option is specified, the core status byte
(XCSR_SB) contained in XCSR[31–24] is returned after the read data. XCSR_SB reflects the state after
the memory write was performed.
The examples show the WRITE_MEM.B{_WS}, WRITE_MEM.W{_WS}, and WRITE_MEM.L{_WS}
commands.
WRITE_MEM.sz
Write memory at the specified address
Non-intrusive
0x10
Address[23-0]
Memory
data[7–0]
host
→
target
host
→
target
host
→
target
D
L
Y
0x14
Address[23-0]
Memory
data[15–8]
Memory
data[7–0]
host
→
target
host
→
target
host
→
target
host
→
target
D
L
Y
0x18
Address[23-0]
Memory
data[31–24]
Memory
data[23–16]
Memory
data[15–8]
Memory
data[7–0]
host
→
target
host
→
target
host
→
target
host
→
target
host
→
target
host
→
target
D
L
Y
WRITE_MEM.sz_WS
Write memory at the specified address with status
Non-intrusive
0x11
Address[23-0]
Memory
data[7–0]
XCSR_SB
host
→
target
host
→
target
host
→
target
D
L
Y
target
→
host
0x15
Address[23-0]
Memory
data[15–8]
Memory
data[7–0]
XCSR_SB
host
→
target
host
→
target
host
→
target
host
→
target
D
L
Y
target
→
host
0x19
Address[23-0]
Memory
data[31–24]
Memory
data[23–16]
Memory
data[15–8]
Memory
data[7–0]
XCSR_SB
host
→
target
host
→
target
host
→
target
host
→
target
host
→
target
host
→
target
D
L
Y
target
→
host
