ColdFire Core
Freescale Semiconductor
7-11
MCF51CN128 Reference Manual, Rev. 6
All ColdFire processors use an instruction restart exception model. Exception processing includes all
actions from fault condition detection to the initiation of fetch for first handler instruction. Exception
processing is comprised of four major steps:
1. The processor makes an internal copy of the SR and then enters supervisor mode by setting the S
bit and disabling trace mode by clearing the T bit. The interrupt exception also forces the M bit to
be cleared and the interrupt priority mask to set to current interrupt request level.
3. The processor saves the current context by creating an exception stack frame on the system stack.
The exception stack frame is created at a 0-modulo-4 address on top of the system stack pointed to
by the supervisor stack pointer (SSP). As shown in
, the processor uses a simplified
fixed-length stack frame for all exceptions. The exception type determines whether the program
counter placed in the exception stack frame defines the location of the faulting instruction (fault)
or the address of the next instruction to be executed (next).
4. The processor calculates the address of the first instruction of the exception handler. By definition,
the exception vector table is aligned on a 1 MB boundary. This instruction address is generated by
fetching an exception vector from the table located at the address defined in the vector base register.
The index into the exception table is calculated as (4
×
vector number). After the exception vector
has been fetched, the vector contents determine the address of the first instruction of the desired
handler. After the instruction fetch for the first opcode of the handler has initiated, exception
processing terminates and normal instruction processing continues in the handler.
The table contains 256 exception vectors; the first 64 are defined for the core and the remaining 192 are
device-specific peripheral interrupt vectors. See
Chapter 8, “Interrupt Controller (CF1_INTC)”
for details
on the device-specific interrupt sources.
For the V1 ColdFire core, the table is partially populated with the first 64 reserved for internal processor
exceptions, while vectors 64-102 are reserved for the peripheral I/O requests and the seven software
interrupts. Vectors 103–255 are unused and reserved.
Table 7-6. Exception Vector Assignments
Vector
Number(s)
Vector
Offset (Hex)
Stacked
Program
Counter
Assignment
0
0x000
—
Initial supervisor stack pointer
1
0x004
—
Initial program counter
2. The processor determines the exception vector number. For all faults except interrupts, the
processor performs this calculation based on exception type. For interrupts, the processor
performs an interrupt-acknowledge (IACK) bus cycle to obtain the vector number from the
interrupt controller if CPUCR[IAE] is set. The IACK cycle is mapped to special locations within
the interrupt controller’s address space with the interrupt level encoded in the address. If
CPUCR[IAE] is cleared, the processor uses the vector number supplied by the interrupt controller
at the time the request was signaled for improved performance.
All ColdFire processors support a 1024-byte vector table aligned on any 1 MB address boundary (see
). For the V1 ColdFire core, the only practical locations for the vector table are based at
0x(00)00_0000 in the flash or 0x(00)80_0000 in the internal SRAM.
