NXP Semiconductors freescale semiconductor ColdFire MCF51CN128 Series, Справочное руководство

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Mini-FlexBus
Freescale Semiconductor 11-20
MCF51CN128 Reference Manual, Rev. 6
In addition to address setup, a programmable address hold option for each chip select exists. Address and
attributes can be held one to four clocks after chip-select, byte-selects, and output-enable negate.
Figure 11-20 and Figure 11-21 show read and write bus cycles with two clocks of address hold.
Figure 11-20. Read Cycle with Two-Clock Address Hold (No Wait States)
Figure 11-21. Write Cycle with Two-Clock Address Hold (No Wait States)
FB_CLK
FB_R/W
FB_ALE
S0 S1 S2 S3 AH
DATA
DATA
Mux’d Bus
Non-Mux’d Bus
FB_A[19:0]
ADDR[19:8]
ADDR[19:8]
FB_D[7:0]
ADDR[ X :0]
FB_AD[19:8]
FB_AD[ X :0]
FB_CS n , FB_OE
S0
FB_CLK
FB_R/W
FB_ALE
FB_OE
S0 S1 S2 S3 AH
DATA
DATA
Mux’d Bus
Non-Mux’d Bus
FB_A[19:0]
ADDR[19:0]
FB_D[7:0]
ADDR[ X :0]
FB_AD[19: X+1 ]
ADDR[19: X+1 ]
FB_AD[ X :0]
FB_CS n
S0