Multipurpose Clock Generator (MCG)
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
6-15
6.4.4
Bus Frequency Divider
The BDIV bits can be changed at anytime and the actual switch to the new frequency occurs immediately.
6.4.5
Low Power Bit Usage
The low power bit (LP) is provided to allow the FLL or PLL to be disabled and thus conserve power when
these systems are not being used. The DRS bit can not be written while LP bit is 1.However, in some
applications it may be desirable to enable the FLL or PLL and allow it to lock for maximum accuracy
before switching to an engaged mode. Do this by writing the LP bit to 0.
6.4.6
Internal Reference Clock
When IRCLKEN is set, the internal reference clock signal is presented as MCGIRCLK, which can be used
as an additional clock source. The MCGIRCLK frequency can be re-targeted by trimming the period of
the internal reference clock. This can be done by writing a new value to the TRIM bits in the MCGTRM
register. Writing a larger value decreases the MCGIRCLK frequency, and writing a smaller value to the
MCGTRM register increases the MCGIRCLK frequency. The TRIM bits affects the MCGOUT frequency
if the MCG is in FLL engaged internal (FEI), FLL bypassed internal (FBI), or bypassed low power internal
(BLPI) mode. The TRIM and FTRIM value is initialized by POR but is not affected by other resets.
If IREFSTEN and IRCLKEN bits are set, the internal reference clock keeps running during stop mode to
provide a fast recovery upon exiting stop.
All MCU devices are factory programmed with a trim value in a reserved memory location. This value can
be copied to the MCGTRM register during reset initialization. The factory trim value does not include the
FTRIM bit. For finer precision, the user can trim the internal oscillator in the application and set the
FTRIM bit accordingly.
6.4.7
External Reference Clock
The MCG module can support an external reference clock with frequencies between 31.25 kHz to 40 MHz
in all modes. When ERCLKEN is set, the external reference clock signal is presented as MCGERCLK,
which can be used as an additional clock source. When IREFS = 1, the external reference clock is not used
by the FLL or PLL and is only used as MCGERCLK. In these modes, the frequency can be equal to the
maximum frequency the chip-level timing specifications supports (see
”).
If EREFSTEN and ERCLKEN bits are set or the MCG is in FEE, FBE, PEE, PBE or BLPE mode, the
external reference clock keeps running during stop mode to provide a fast recovery upon exiting stop.
If CME bit is written to 1, the clock monitor is enabled. If the external reference falls below a certain
frequency (f
loc_high
or f
loc_low
depending on the RANGE bit in the MCGC2), the MCU resets. The LOC
bit in the System Reset Status (SRS) register is set to indicate the error.
