Pins and Connections
MCF51CN128 Reference Manual, Rev. 6
2-34
Freescale Semiconductor
microcontroller’s BDC clock could be as fast as the bus clock rate, so there should never be any significant
capacitance connected to the BKGD/MS pin that could interfere with background serial communications.
Although the BKGD/MS pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speed-up pulses to ensure fast rise times. Small capacitances from
cables and the absolute value of the internal pullup device play almost no role in determining rise and fall
times on the BKGD/MS pin.
The BKGD/MS select pin can be reprogrammed to operate as one of the Rapid GPIO pins on this device,
or as a standard GPIO. It should only be programmed for use as an output, as an external signal driving
this pin during startup may cause the device to boot into debug mode.
2.4.6
ADC Reference Pins (V
REFH
, V
REFL
)
V
REFH
and V
REFL
are the voltage reference high and low inputs, respectively, for the ADC module. These
are internally connected to V
DDA
and V
SSA
, and are not present as explicit pins on the device.
2.4.7
General-Purpose I/O and Peripheral Ports
The MCF51CN128 series microcontrollers support up to 70 general-purpose I/O pins
1
, which are shared
with on-chip peripheral functions (timers, serial I/O, ADC, etc.).
When a port pin is configured as a general-purpose output or a peripheral uses the port pin as an output,
software can select one of two drive strengths and enable or disable slew rate control.
When a port pin is configured as a general-purpose input or a peripheral uses the port pin as an input,
software can enable a pull-up device. Pad cells on these devices also include an optional low pass filter in
the inputs. Again, this can be enabled via software control.
Immediately after reset, these pins (excluding the RESET and BKGD/MS pins) are configured as
high-impedance general-purpose inputs with internal pull-up devices disabled.
When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is
read from the port data registers, even though the peripheral controls the pin direction via the pin’s output
buffer enable. For information about controlling these pins as general-purpose I/O pins, see “
“Parallel Input/Output Control
NOTE
To avoid extra current drain from floating input pins, the reset initialization
routine in the application program should enable on-chip pullup devices or
change the direction of unused pins to outputs so they do not float.
1. There are restrictions on the use of RESET and BKGD/MS as GPIO. See those sections for details.
