Multipurpose Clock Generator (MCG)
MCF51CN128 Reference Manual, Rev. 6
6-10
Freescale Semiconductor
6.3.6
MCG Control Register 4 (MCGC4)
4
DIV32
Divide-by-32 Enable
— Controls an additional divide-by-32 factor to the external reference clock for the FLL
when RANGE bit is set. When the RANGE bit is 0, this bit has no effect. Writes to this bit are ignored if PLLS bit
is set.
0 Divide-by-32 is disabled.
1 Divide-by-32 is enabled when RANGE=1.
3:0
VDIV
VCO Divider
— Selects the amount to divide down the VCO output of PLL. The VDIV bits establish the
multiplication factor (M) applied to the reference clock frequency.
0000 Encoding 0 — Reserved.
0001 Encoding 1 — Multiply by 4.
0010 Encoding 2 — Multiply by 8.
0011 Encoding 3 — Multiply by 12.
0100 Encoding 4 — Multiply by 16.
0101 Encoding 5 — Multiply by 20.
0110 Encoding 6 — Multiply by 24.
0111 Encoding 7 — Multiply by 28.
1000 Encoding 8 — Multiply by 32.
1001 Encoding 9 — Multiply by 36.
1010 Encoding 10 — Multiply by 40.
1011 Encoding 11 — Multiply by 44.
1100 Encoding 12 — Multiply by 48.
1101 Encoding 13 — Reserved (default to M=48).
111x Encoding 14-15 — Reserved (default to M=48).
7
6
5
4
3
2
1
0
R
0
0
DMX32
0
0
0
DRST
W
DRS
Reset:
0
0
0
0
0
0
0
0
Figure 6-7. MCG Control Register 4 (MCGC4)
Table 6-7. MCG PLL Register Field Descriptions (continued)
Field
Description
