Mini-FlexBus
11-21
Freescale Semiconductor
MCF51CN128 Reference Manual, Rev. 6
shows a bus cycle using address setup, wait states, and address hold.
Figure 11-22. Write Cycle with Two-Clock Address Setup and
Two-Clock Hold (One Wait State)
11.4.7
Bus Errors
There are certain accesses to the Mini-FlexBus that cause the system bus to hang. It is important to have
a good access-error handler to manage these conditions.
One such access is if CSCR
n
[AA] is cleared, the system hangs. Four other types of accesses cause the
access to terminate with a bus error.
•
Mini-Flexbus module disabled using the platform peripheral power management control.
Mini-FlexBus accesses cause an error termination on the bus and prohibit the access to the
Mini-FlexBus.
•
Attempted writes to space defined as write protected (CSMR
n
[WP] is set) are terminated with an
error response and the access is inhibited to the Mini-FlexBus.
•
Mini-FlexBus access not hitting in either chip select region is terminated with an error response
and the access is inhibited to the Mini-FlexBus.
•
Mini-FlexBus access hitting in both chip select regions is terminated with an error response and
the access is inhibited to the Mini-FlexBus
FB_CLK
FB_R/W
FB_ALE
FB_OE
S0
AS
S1
WS
S2
S3
AH
DATA
DATA
Mux’d Bus
Non-Mux’d Bus
FB_A[19:0]
ADDR[19:0]
FB_D[7:0]
ADDR[
X
:0]
FB_AD[19:
X+1
]
ADDR[19:
X+1
]
FB_AD[
X
:0]
FB_CS
n
S0
