Multipurpose Clock Generator (MCG)
MCF51CN128 Reference Manual, Rev. 6
6-16
Freescale Semiconductor
6.4.8
Fixed Frequency Clock
The MCG presents the divided reference clock as MCGFFCLK for use as an additional clock source. The
MCGFFCLK frequency must be no more than 1/4 of the MCGOUT frequency to be valid. This clock is
intended for use in systems that include a USB interface. It allows the MCG to supply a 48MHz clock to
the USB. This same clock can be used to derive MCGOUT. Alternately, MCGOUT can be derived from
internal or external reference clock. This allows the CPU to run at a lower frequency (to conserve power)
while the USB continues to monitor traffic.
The FLL can not be used for generation of the system clocks while the PLL is supplying MCGPLLSCLK.
6.5
Initialization / Application Information
This section describes how to initialize and configure the MCG module in application. The following
sections include examples on how to initialize the MCG and properly switch between the various available
modes.
6.5.1
MCG Module Initialization Sequence
The MCG comes out of reset configured for FEI mode with the BDIV set for divide-by-2. The internal
reference stabilizes in t
irefst
microseconds before the FLL can acquire lock. As soon as the internal
reference is stable, the FLL acquires lock in t
fll_acquire
milliseconds.
NOTE
If the internal reference is not already trimmed, the BDIV value should not
be changed to divide-by-1 without first trimming the internal reference.
Failure to do so could result in the MCU running out of specification.
6.5.1.1
Initializing the MCG
Because the MCG comes out of reset in FEI mode, the only MCG modes that can be directly switched to
upon reset are FEE, FBE, and FBI modes (see
). Reaching any of the other modes requires first
configuring the MCG for one of these three initial modes. Care must be taken to check relevant status bits
in the MCGSC register reflecting all configuration changes within each mode.
To change from FEI mode to FEE or FBE modes, follow this procedure:
1. Enable the external clock source by setting the appropriate bits in MCGC2.
2. If the RANGE bit (bit 5) in MCGC2 is set, set DIV32 in MCGC3 to allow access to the proper
RDIV values.
3. Write to MCGC1 to select the clock mode.
— If entering FEE mode, set RDIV appropriately, clear the IREFS bit to switch to the external
reference, and leave the CLKS bits at %00 so that the output of the FLL is selected as the
system clock source.
— If entering FBE, clear the IREFS bit to switch to the external reference and change the CLKS
bits to %10 so that the external reference clock is selected as the system clock source. The
