Modes of Operation
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
3-3
Table 3-2. CPU / Power Mode Selections
Mode of Operation
SOPT1
SIM
XCSR
BDC
SPMSC1
PMC
SPMSC2
PMC
CPU and
Peripheral
Clocks
Effects on Sub-System
ST
OPE
WA
IT
E
ENBDM
1
1
ENBDM is located in the upper byte of the XCSR register which is write-accessible only through BDC commands. See
20.3.2, “Extended Configuration/Status Register (XCSR)”.
LV
D
E
LV
D
S
E
LPR
PPDC
BDC Clock
Switche
d
Power
Run mode
- processor and peripherals
clocked normally.
x
x
x
x
x
0
x
On. MCG in any
mode
On
Note:
When not
needed, the BDC
clock can be gated
off at the discretion
of the processor.
The clock is
available within a
few cycles of
demand by the
processor,
normally when a
negative edge is
detected on
BKGD. The BDM
command
associated with
that negative edge
may not take
affect.
On
x
1
1
x
x
1
x
x
x
x
LPrun mode with low voltage detect
disabled
2
- processor and peripherals
clocked at low frequency
3
.
Low voltage detects are not active.
2
If a device is in low power run mode, a falling edge on an active BKGD/MS pin exits low power run mode, clears the LPRS bits
and returns the device to normal run mode.
3
In LPrun maximum 250 kHz CPU frequency and 125 kHz peripheral clock frequency.
x
x
0
0
x
1
0
Low freq required.
MCG in BLPE
mode.
Loose Reg
0
1
0
Wait mode
- processor clock nominally
inactive, but peripherals are clocked.
x
1
x
x
x
0
x
Periph clocks on.
CPU clock on if
XCSR[ENBDM]=1
.
On
x
1
1
x
x
1
x
x
x
x
On
LPwait mode
- processor clock is
inactive, peripherals are clocked at low
frequency and the PMC is loosely
regulating.
Low voltage detects are not active.
x
1
0
0
x
1
0
CPU clock is off.
Periph clocks at
low speed.
MCG in BLPE.
Loose Reg
1
0
Stop modes disabled
; Illegal opcode
reset if STOP instruction executed and
CPUCR[IRD] is cleared, else illegal
instruction exception is generated.
0
0
Function
of BKGD/
MS at
reset
1
1
0
0
On
Function of
BKGD/MS at reset
On
Stop4
- Either low-power modes have
not been requested, or low voltage
detects are enabled or
XCSR[ENBDM] = 1.
1
0
x
x
x
0
0
Peripheral clocks
off. CPU clock on if
XCSR[ENBDM]=1
.
BDC clock enabled
only if
XCSR[ENBDM]=1
prior to entering
stop.
On
x
1
1
1
0
x
1
1
0
1
1
x
x
x
x
CPU clock on.
Periph clocks off.
Stop3
- Low voltage detect in stop is not
enabled. Clocks must be at low
frequency and are gated. The regulator
is in loose regulation.
1
0
0
1
0
X
0
Low freq required.
MCG in BLPE
mode. CPU clock
off. Some
peripheral clocks
are optionally on.
See
for
details.
Off
Loose Reg
0
x
Stop2
- Low voltage detects are not
active. If BDC is enabled, stop4 is
invoked rather than stop2.
1
0
1
0
0
1
N/A
N/A
Off
0
x
