Hitachi H8/3060, Руководство по оборудованию

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557
End of erasing
Start
Set SWE bit in FLMCR1
Set ESU bit in FLMCR1
Set E bit in FLMCR1
Wait (t
sswe
)
µ
s
Wait (t
sesu
)
µ
s
n = 1
Set EBR1 or EBR2
Enable WDT
*
3,
*
4
* 5
* 5
*
5
* 5
* 5
* 5
* 5
* 5 * 5
*
5
*
5
* 5
Wait (t
se
) ms
Wait (t
ce
)
µ
s
Wait (t
cesu
)
µ
s
Wait (t
sev
)
µ
s
Set block start address as verify address
Wait (t
sevr
)
µ
s
* 2
Wait (t
cev
)
µ
s
Start of erase
Clear E bit in FLMCR1
Clear ESU bit in FLMCR1
Set EV bit in FLMCR1
H'FF dummy write to verify address
Read verify data
Clear EV bit in FLMCR1
Wait (t
cev
)
µ
s
Clear EV bit in FLMCR1
Re-erase
Clear SWE bit in FLMCR1
Disable WDT
End of erase
* 1
Verify data = all 1s?
Last address of block?
Erase failure
Clear SWE bit in FLMCR1
n
≥
N?
No
No
No
Yes
Yes
Yes
n
←
n + 1
Increment
address
Wait (t
cswe
)
µ
s Wait (t
cswe
)
µ
s
Notes:
*
1 Prewriting (setting erase block data to all 0s) is not necessary.
* 2 Verify data is read in 16-bit (word) units.
* 3 Make only a single-bit specification in the erase block registers (EBR1 and EBR2). Two or more bits must not be set simultaneously.
* 4 Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn.
*
5 The wait times and the value of N are shown in section 22.3.6, Flash Memory Characteristics.
Perform erasing in block units.
Figure 18.11 Erase/Erase-Verify Flowchart (Single-Block Erasing)