GE Digital Energy L60, Инструкция по эксплуатации

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3-34 L60 LINE PHASE COMPARISON SYSTEM – INSTRUCTION MANUAL
DIRECT INPUT AND OUTPUT COMMUNICATIONS CHAPTER 3: INSTALLATION
3
source. As a result, data sampling for both of the UR RS422 channels is synchronized via the send timing leads on data
module 1, shown as follows. If the terminal timing feature is not available or this type of connection is not wanted, the
G.703 interface is a viable option that does not impose timing restrictions.
Figure 3-39: Timing configuration for RS422 two-channel, three-terminal application
Data module 1 provides timing to the L60 RS422 interface via the ST(A) and ST(B) outputs. Data module 1 also provides
timing to data module 2 TT(A) and TT(B) inputs via the ST(A) and AT(B) outputs. The data module pin numbers have been
omitted in the figure because they vary by manufacturer.
3.4.5.3 Transmit timing
The RS422 interface accepts one clock input for transmit timing. It is important that the rising edge of the 64 kHz transmit
timing clock of the multiplexer interface is sampling the data in the center of the transmit data window. Therefore, it is
important to confirm clock and data transitions to ensure proper system operation. For example, the following figure
shows the positive edge of the Tx clock in the center of the Tx data bit.
Figure 3-40: Clock and data transitions
Data module 1
Data module 2
Signal name
Signal name
SD(A) - Send data
TT(A) - Terminal timing
TT(B) - Terminal timing
SD(B) - Send data
RD(A) - Received data
RD(A) - Received data
SD(A) - Send data
SD(B) - Send data
RD(B) - Received data
RD(B) - Received data
RS(A) - Request to send (RTS)
RS(A) - Request to send (RTS)
RT(A) - Receive timing
CS(A) - Clear To send
CS(A) - Clear To send
RT(B) - Receive timing
CS(B) - Clear To send
CS(B) - Clear To send
Local loopback
Local loopback
Remote loopback
Remote loopback
Signal ground
Signal ground
ST(A) - Send timing
ST(A) - Send timing
ST(B) - Send timing
ST(B) - Send timing
RS(B) - Request to send (RTS)
RS(B) - Request to send (RTS)
831022A3.CDR
W 7a
W 2b
W 8a
7W
Shld.
Shld.
Tx1(+)
Tx2(+)
Tx1(-)
Tx2(-)
Rx1(+)
Rx2(+)
+
com
Rx1(-)
Rx2(-)
–
INTER-REL
A
Y
C
OMMUNICA
TIONS
W 3a
W 5b
W 5a
W 3b
W 2a
W 6a
W 6b
W 7b
W 8b
W 4b
W 4a
RS422
CHANNEL 1
RS422
CHANNEL 2
CLOCK
SURGE
831733A1.CDR
Tx Clock
Tx Data