XRT86VL38
PRELIMINARY
xr
OCTAL T1/E1/J1 FRAMER/LIU COMBO
REV. P1.0.6
363
After the payload bits of Timeslot 0 of all four channels are sent, it comes the payload bits of Timeslot 1 of
Channel 0 and so on. The table below demonstrates how payload bits of four channels are mapped into
one 16.384Mbit/s data stream
X
Y
: The Xth payload bit of Channel Y
2.
When the framer is running at HMVIP or H100 16.384MBit/s byte-mulitplexed mode, signaling information
is inserted from the TxSig/TSb[0] pin or from the TSCR register (0xn340-n35F).
When the local terminal is sending the fifth payload bit of one channel, signaling bit A of that
corresponding channel is repeated and sent through the TxSig/TSb[0] pin; Similarly, signaling bit B, C,
and D of the corresponding channel is repeated and sent through the TxSig/TSb[0] pin when the local
terminal is providing the sixth, seventh, and eighth payload bit respectively, as shown in Figure 77.
3.
After the first octet of all four channels are sent, the local Terminal Equipment start sending the second
octets following the same rules of Step 1 and 2.
For HMVIP mode, the Transmit Single-frame Synchronization signal should pulse HIGH for four clock cycles
(the last two bit positions of the previous multiplexed frame and the first two bits of the next multiplexed frame)
indicating frame boundary of the multiplexed data stream. For H100 mode, the Transmit Single-frame
Synchronization signal should pulse HIGH for two clock cycles (the last bit position of the previous multiplexed
frame and the first bit position of the next multiplexed frame). The Transmit Single-frame Synchronization
signal of Channel 0 pulses HIGH to identify the start of multiplexed data stream of Channel 0-3. The Transmit
Single-frame Synchronization signal of Channel 4 pulses HIGH to identify the start of multiplexed data stream
of Channel 4-7. By sampling the HIGH pulse on the Transmit Single-frame Synchronization signal, the framer
can position the beginning of the multiplexed E1 frame. It is responsibility of the Terminal Equipment to align
the multiplexed transmit serial data with the Transmit Single-frame Synchronization pulse.
Inside the framer, all the "don't care" bits will be stripped away. The framing bits, signaling and payload data are
de-multiplexed inside the XRT86VL38 device and send to each individual channel. These data will be
processed by each individual framer and send to LIU interface. The local Terminal Equipment provides a free-
running 2.048MHz clock to the Transmit Serial Input clock of each channel. The framer will use this clock to
carry the processed payload and signaling data to the transmit section of the device.
See Figure 75 below for how to interface the local Terminal Equipment with the Transmit Payload Data Input
Interface block of the framer in HMVIP or H100 16.384Mbit/s mode. Figure 77 shows the timing signals when
the framer is running at HMVIP or H100 16.384 MHz mode.
B
IT
0
B
IT
1
B
IT
2
B
IT
3
B
IT
4
B
IT
5
B
IT
6
B
IT
7
1
0
1
0
2
0
2
0
3
0
3
0
4
0
4
0
B
IT
0
B
IT
1
B
IT
2
B
IT
3
B
IT
4
B
IT
5
B
IT
6
B
IT
7
1
1
1
1
2
1
2
1
3
1
3
1
4
1
4
1
B
IT
0
B
IT
1
B
IT
2
B
IT
3
B
IT
4
B
IT
5
B
IT
6
B
IT
7
1
2
1
2
2
2
2
2
3
2
3
2
4
2
4
2
B
IT
0
B
IT
1
B
IT
2
B
IT
3
B
IT
4
B
IT
5
B
IT
6
B
IT
7
1
3
1
3
2
3
2
3
3
3
3
3
4
3
4
3
