Argantix XDS 100-100, Руководство пользователя и программирования

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User and Programming Manual
110 XDS Series
13.2 Standard Event Status Group
This group consists of an Event register and an Enable register that are programmed by Common
commands. The Standard Event register latches events relating to interface communication status. It
is a read-only register that is cleared when read. The Standard Event Enable register functions
similarly to the enable registers of the Operation and Questionable status groups.
Command Action
*ESE programs specific bits in the Standard Event Enable register.
*ESR? reads and clears the Standard Event register.
The PON bit in the Standard Event register is set whenever the Power supply is turned on.
13.3 Status Byte Register
This register summarizes the information from all other status groups as defined in the IEEE 488.2
Standard Digital Interface for Programmable Instrumentation. The bit configuration is shown in Table
11-7.
Command Action
*STB? reads the data in the register but does not clear it (returns MSS in bit 6)
The MSS Bit
This is a real-time (unlatched) summary of all Status Byte register bits that are enabled by the
Service Request Enable register. MSS is set whenever the Power supply has one or more reasons
for needing service. *STB? reads the MSS in bit position 6 of the response but does not clear any of
the bits in the Status Byte register.
The MAV bit and Output Queue
The Output Queue is a first-in, first-out (FIFO) data register that stores Power supply-to-controller
messages until the controller reads them. Whenever the queue holds one or more bytes, it sets the
MAV bit (bit 4) of the Status byte register.