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Model 8/[F:8] Registers
33
23913A/0—November 2000
Embedded AMD-K6™ Processors BIOS Design Guide
Preliminary Information
Examples
Suppose that the range of memory from 16 Mbytes to 32 Mbytes
is uncacheable, and the 8-Mbyte range of memory on top of 1
G by t e i s w r i t e - c o m b i nab l e . R a n g e 0 i s d e f i n e d a s t he
uncacheable range, and range 1 is defined as the write-
combining range.
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Extracting the 15 most-significant bits of the 32-bit physical
base address that corresponds to 16 Mbytes (0100_0000h)
yields a physical base address 0 field of
000_0000_1000_0000b. Because the uncacheable range size
is 16 Mbytes, the physical mask value 0 field is
111_1111_1000_0000b, according to Table 16 on page 32. Bit
1 of the UWCCR register (WC0) is set to 0, and bit 0 of the
UWCCR register is set to 1 (UC0).
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Extracting the 15 most-significant bits of the 32-bit physical
base address that corresponds to 1 Gbyte (4000_0000h)
yields a physical base address 1 field of
010_0000_0000_0000b. Because the write-combining range
size is 8 Mbytes, the physical mask value 1 field is
111_1111_1100_0000b, according to Table 16. Bit 33 of the
UWCCR register (WC1) is set to 1 and bit 32 of the UWCCR
register is set to 0 (UC1).