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Appendix A
Embedded AMD-K6™ Processors BIOS Design Guide
23913A/0—November 2000
Preliminary Information
Function 8000_0005h — L1 Cache Information
Input:
EAX = 8000_0005h
Output:
EAX = Reserved
EBX = TLB Information
ECX = L1 Data Cache Information
EDX = L1 Instruction Cache Information
Function 8000_0005h returns information about the processor’s on-chip L1 caches and
associated TLBs. Tables 33, 34, and 35 provide the format for the information returned
by the 8000_0005h function.
Table 33.
EBX Format Returned by Function 8000_0005h
Data TLB
Instruction TLB
Associativity
1
Notes:
1. See “Associativity for L1 Caches and L1 TLBs” on page 80 for more information.
# Entries
Associativity
1
# Entries
EBX
Bits 31–24
Bits 23–16
Bits 15–8
Bits 7–0
Table 34.
ECX Format Returned by Function 8000_0005h
L1 Data Cache
Size (Kbytes)
Associativity
1
Notes:
1. See “Associativity for L1 Caches and L1 TLBs” on page 80 for more information
Lines per Tag
Line Size (bytes)
ECX
Bits 31–24
Bits 23–16
Bits 15–8
Bits 7–0
Table 35.
EDX Format Returned by Function 8000_0005h
L1 Instruction Cache
Size (Kbytes)
Associativity
1
Notes:
1. See “Associativity for L1 Caches and L1 TLBs” on page 80 for more information.
Lines per Tag
Line Size (bytes)
EDX
Bits 31–24
Bits 23–16
Bits 15–8
Bits 7–0