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Processor Models and Steppings
Embedded AMD-K6™ Processors BIOS Design Guide
23913A/0—November 2000
Preliminary Information
Processor Models and Steppings
Four models within the AMD-K6 family of processors —models
7, 8, 9, and D—are discussed in this document.
For most models, feature and function detection can be
determined by reading the standard and extended feature bits
by executing the CPUID instruction. However, for certain
models, it is necessary to check the stepping—by executing the
CPUID instruction—to determine specific function support.
Table 1 shows the features of each model and stepping of the
AMD-K6 processor family.
The descriptions in the remainder of this section provide more
de tailed info rmatio n on the A MD-K6 processor family
members, and the models and steppings that comprise each
member.
Table 7 on page 14 and Table 8 on page 15 summarize the MSR
differences between the models and steppings of the AMD-K6
family of processors.
Table 1.
Features of the AMD-K6™ Processor Family
Processor
Model/
Stepping
Process (in
microns)
Number
of MSRs
1
Notes:
1. Refer to “Model-Specific Registers Overview” on page 14 for more information.
3DNow!™
Instructions
3DNow!
Extensions
AMD PowerNow!™
Technology
L2
Cache
AMD-K6E
7
0.25
6
AMD-K6-2
8/[7:0]
0.25
7
Yes
AMD-K6-2 and
AMD-K6-2E
8/[F:8]
0.25
10
2
2. Model 8/[F:8] defines the bits and fields in the Write Handling Control Register (WHCR) and Extended Feature Enable Register (EFER)
differently from the models 7 and 8/[7:0].
Yes
AMD-K6-2E+
D/[7:4]
0.18
11
3,4
3. This model implements the same ten MSRs as the Model 8/[F:8]. With the exception of bit 4 (L2D) in the EFER register, the bits and
fields within these ten MSRs are defined identically.
4. Low-power versions implement one additional register to support AMD PowerNow!™ technology.
Yes
Yes
Yes
5
5. AMD PowerNow! technology is supported on low-power versions of these processors only.
128 Kbytes
AMD-K6-
III
9/[3:0]
0.25
11
3
Yes
256 Kbytes
AMD-K6-
III
E+
D/[3:0]
0.18
11
3,4
Yes
Yes
Yes
5