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46
Model D Registers
Embedded AMD-K6™ Processors BIOS Design Guide
23913A/0—November 2000
Preliminary Information
Processor State Observability Register (PSOR) (Low-Power Versions)
The low-power versions of the AMD-K6-2E+ and AMD-K6-IIIE+
processors provide the Processor State Observability Register
(PSOR) as defined in Figure 17.
Note: Standard-power versions of Model D support the PSOR as
defined on page 34.
The PSOR register is MSR C000_0087h.
.
Figure 17.
Processor State Observability Register (PSOR
) (Model D Low-Power Versions)
PBF[2:0] Field
This read-only field contains the BF divisor values externally
applied to the processor BF[2:0] pins. These input BF values are
sampled by the processor during the falling transition of
RESET.
Note: This BF divisor value may be different than the BF divisor
value supplied to the processor’s internal PLL.
VID Field
This read-only field contains the Voltage ID bits driven to the
processor VID[4:0] pins at RESET. These bits are initialized to
01010b and driven on the VID[4:0] pins at RESET.
Note: Low-power AMD-K6-2E+ and AMD-K6-IIIE+ processors
support AMD PowerNow! technology, which enables
dynamic alteration of the processor’s core voltage. See
“Enhanced Power Management Register (EPMR) (Low-
Power Versions)” on page 54 for information on
programming the VID[4:0] pins.
2
0
63
EBF[2:0]
Reserved
Symbol
Description
Bits
NOL2
No L2 Functionality
8
STEP
Processor Stepping
7-4
EBF
Effective Bus Frequency Divisor
2-0
3
4
STEP
7
8
9
N
O
L
2
VID
PBF[2:0]
16
20
23
21
15
24
Symbol
Description
Bits
PBF
Pin Bus Frequency Divisor
23-21
VID
Voltage ID
20-16