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50
Model D Registers
Embedded AMD-K6™ Processors BIOS Design Guide
23913A/0—November 2000
Preliminary Information
Figure 20. L2 Tag or Data Location (AMD-K6™-2E+ Processor)—EDX
Figure 21. L2 Tag or Data Location (AMD-K6™-
III
E+ Processor)—EDX
Reserved
0
Set
21
31
20 19
17 16
5
15
18
Way
4
3 2 1
6
Symbol
Description
Bit
Set
Selects the desired cache set
14-6
Line
Selects Line1 (1) or Line0 (0)
5
Octet
Selects one of four octets
4-3
Dword
Selects upper (1) or lower (0) dword
2
L
i
n
e
Octet
D
w
o
r
d
T
/
D
Symbol
Description
Bit
T/D
Selects Tag (1) or Data (0) access
20
Way
Selects desired cache way
17-16
14
Reserved
0
Set
21
31
20 19
17 16
5
15
18
Way
4
3 2 1
6
Symbol
Description
Bit
Set
Selects the desired cache set
15-6
Line
Selects Line1 (1) or Line0 (0)
5
Octet
Selects one of four octets
4-3
Dword
Selects upper (1) or lower (0) dword
2
L
i
n
e
Octet
D
w
o
r
d
T
/
D
Symbol
Description
Bit
T/D
Selects Tag (1) or Data (0) access
20
Way
Selects desired cache way
17-16