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Model-Specific Registers Overview
15
23913A/0—November 2000
Embedded AMD-K6™ Processors BIOS Design Guide
Preliminary Information
Level-2 Cache Array Access Register
L2AAR
C000_0089h
7, 8
Not supported
9
page 40
D
page 48
Enhanced Power Management Register
EPMR
C000_0086h
7, 8, 9, D
1
Not supported
D
2
page 54
Notes:
1. Standard-power versions only.
2. Low-power versions only.
Table 7.
Summary by Register of MSR Differences within the AMD-K6™ Family (continued)
Register
Mnemonic
ECX Value
Models
Description
Table 8.
Summary by Model of MSR Differences within the AMD-K6™ Family
Model Stepping
Standard
MSRs
1
EFER
2
WHCR
3
STAR UWCCR
PSOR
PFIR L2AAR EPMR
L2D EWBEC DPE SCE
508
MB
4092
MB
BF
PBF
VID
EBF
7
All
X
X
X
8
7:0
X
X
X
X
8
F:8
X
X
X
X
X
X
X
X
X
9
3:0
X
X
X
X
X
X
X
X
X
X
X
D
3:0
7:4
X
X
X
X
X
X
X
X
X
4
X
5
X
X
X
5
Notes:
1. There are four MSRs that every model and stepping of the AMD-K6 family of processors support identically—MCAR, MCTR, TR12, and
TSC.
2. L2D, EWBEC, and DPE are bits/fields supported in EFER for the indicated models/steppings. All models/steppings support the System
Call Extension (SCE) bit in EFER, even if the corresponding SYSCALL and SYSRET instructions and the STAR register are not supported.
3. Indicates whether the WAELIM field supports 508 Mbytes or 4092 Mbytes of memory. The location of the WAE15M bit and the WAELIM
field within the WHCR register differs between the models/steppings that support 508 Mbytes of memory and those that support 4092
Mbytes of memory.
4. Supported on standard-power versions only.
5. Supported on low-power versions only.