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Model-Specific Registers Overview
Embedded AMD-K6™ Processors BIOS Design Guide
23913A/0—November 2000
Preliminary Information
Model-Specific Registers Overview
Each of the models of the AMD-K6 processor family support a
different set of model-specific registers (MSRs). These
differences are summariz ed by register in Table 7. The
differences are summarized by model in Table 8 on page 15,
where an ‘X’ indicates support for a register or field.
The content of ECX selects the MSR to be addressed by the
RDMSR and WRMSR instruction.
Table 7.
Summary by Register of MSR Differences within the AMD-K6™ Family
Register
Mnemonic
ECX Value
Models
Description
Machine-Check Address Register
MCAR
00h
All
page 16
Machine-Check Type Register
MCTR
01h
All
page 16
Test Register 12
TR12
0Eh
All
page 16
Time Stamp Counter
TSC
10h
All
page 16
Extended Feature Enable Register
EFER
C000_0080h
7, 8/[7:0]
page 18
8/[F:8]
page 24
9, D
page 39
Write Handling Control Register
WHCR
C000_0082h
7, 8/[7:0]
page 19
8/[F:8], 9, D
page 27
SYSCALL/SYSRET Target Address Register
STAR
C000_0081h
7
Not supported
8, 9, D
page 22
UC/WC Cacheability Control Register
UWCCR
C000_0085h
7, 8/[7:0]
Not supported
8/[F:8], 9, D
page 30
Processor State Observability Register
PSOR
C000_0087h
7, 8/[7:0]
Not supported
8/[F:8], 9, D
1
page 34
D
2
page 46
Page Flush/Invalidate Register
PFIR
C000_0088h
7, 8/[7:0]
Not supported
8/[F:8], 9, D
page 36