![background image](http://html1.mh-extra.com/html/amd/k6-2-450-mhz-processor/k6-2-450-mhz-processor_application-note_2921586044.webp)
32
Model 8/[F:8] Registers
Embedded AMD-K6™ Processors BIOS Design Guide
23913A/0—November 2000
Preliminary Information
Memory-Range
Restrictions
The following rules regarding the address alignment and size of
each range must be adhered to when programming the physical
base address and physical address mask fields of the UWCCR
register:
■
The minimum size of each range is 128 Kbytes.
■
The physical base address must be aligned on a 128-Kbyte
boundary.
■
The physical base address must be range-size aligned. For
example, if the size of the range is 1 Mbyte, then the
physical base address must be aligned on a 1-Mbyte
boundary.
■
All bits set to 1 in the physical address mask must be
contiguous. Likewise, all bits set to 0 in the physical address
mask must be contiguous. For example:
111_1111_1100_0000b is a valid physical address mask.
111_1111_1101_0000b is invalid.
Table 16 lists the valid physical address masks and the resulting
range sizes that can be programmed in the UWCCR register.
Table 16. Valid Masks and Range Sizes for UWCCR Register
Masks
Size
111_1111_1111_1111b
128 Kbytes
111_1111_1111_1110b
256 Kbytes
111_1111_1111_1100b
512 Kbytes
111_1111_1111_1000b
1 Mbyte
111_1111_1111_0000b
2 Mbytes
111_1111_1110_0000b
4 Mbytes
111_1111_1100_0000b
8 Mbytes
111_1111_1000_0000b
16 Mbytes
111_1111_0000_0000b
32 Mbytes
111_1110_0000_0000b
64 Mbytes
111_1100_0000_0000b
128 Mbytes
111_1000_0000_0000b
256 Mbytes
111_0000_0000_0000b
512 Mbytes
110_0000_0000_0000b
1 Gbyte
100_0000_0000_0000b
2 Gbytes
000_0000_0000_0000b
4 Gbytes