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Model 9 Registers
Embedded AMD-K6™ Processors BIOS Design Guide
23913A/0—November 2000
Preliminary Information
When the L2AAR is read or written, EDX is left unchanged.
This facilitates multiple accesses when testing the entire
cache/tag array.
If the L2 cache data is read (as opposed to reading the tag
information), the result (dword) is placed in EAX in the format
as illustrated in Figure 14. Similarly, if the L2 cache data is
written, the write data is taken from EAX.
Figure 14. L2 Data—EAX
If the L2 tag is read (as opposed to reading the cache data), the
result is placed in EAX in the format as illustrated in Figure 15
on page 43. Similarly, if the L2 tag is written, the write data is
taken from EAX.
When accessing the L2 tag, the Line, Octet, and Dword fields of
the EDX register are ignored.
Table 21. Tag versus Data Selector
Instruction
T/D
(EDX[20])
Operation
RDMSR
0
Read dword from L2 data array into EAX. Dword location
is specified by EDX.
RDMSR
1
Read tag, line state and LRU information from L2 tag array
into EAX. Location of tag is specified by EDX.
WRMSR
0
Write dword to the L2 data array using data in EAX. Dword
location is specified by EDX.
WRMSR
1
Write tag, line state and LRU information into L2 tag array
from EAX. Location of tag is specified by EDX.
0
31
Data