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Appendix A
Embedded AMD-K6™ Processors BIOS Design Guide
23913A/0—November 2000
Preliminary Information
Cache Associativity Field Definitions
This section describes the values returned in the associativity fields.
Associativity for L1
Caches and L1 TLBs
The associativity fields for the L1 data cache, L1 instruction
cache, L1 data TLB, and L1 instruction TLB are all 8 bits wide.
Except for 00h (Reserved) and FFh (Full), the number returned
in the associativity field represents the actual number of ways,
with a range of 01h through FEh. For example, a returned value
of 02h indicates 2-way associativity and a returned value of 04h
indicates 4-way associativity.
Associativity for L2
Cache
The associativity field for the L2 cache is 4 bits wide. Table 38
shows the value returned in the associativity field.
Table 38.
Associativity Values for L2 Cache
Bits 15–12
Associativity
0000b
L2 off
0001b
Direct-mapped
0010b
2-way
0011b
Reserved
0100b
4-way
0101b
Reserved
0110b
8-way
0111b
Reserved
1000b
16-way
1001b
Reserved
1010b
Reserved
1011b
Reserved
1100b
Reserved
1101b
Reserved
1110b
Reserved
1111b
Full