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Model 8/[F:8] Registers
Embedded AMD-K6™ Processors BIOS Design Guide
23913A/0—November 2000
Preliminary Information
Figure 6. Write Handling Control Register (WHCR) (Models 8/[F:8], 9, and D)
Write Allocate Enable
Limit Field
The WAELIM field is 10 bits wide. This field, multiplied by 4
Mbytes, defines an upper memory limit. Any pending write
cycle that misses the L1 cache and that addresses memory
below this limit causes the processor to perform a write allocate
(assuming the address is not within a range where write
allocates are disallowed).
Write allocate is disabled for memory accesses at and above this
limit unless the processor determines a pending write cycle is
c ache ab le by m ea n s o f one o f t he o th e r w rite allo ca te
mechanisms — “Write to a Cacheable Page” and “Write to a
Sector” (for more information, see the “Cache Organization”
chapter in the appropriate AMD-K6 or AMD-K6E processor
data sheet.
The maximum value of this limit is ((2
10
–1) · 4 Mbytes) = 4092
Mbytes. When all the bits in this field are set to 0, all memory is
above this limit and the write allocate mechanism is disabled
(even if all bits in the WAELIM field are set to 0, write allocates
can still occur due to the “Write to a Cacheable Page” and
“Write to a Sector” mechanisms).
Once the BIOS determines the amount of RAM installed in the
system, this number should also be used to program the
WAELIM field. For example, a system with 32 Mbytes of RAM
w o u l d p r o g r a m t h e WA E L I M f i e l d w i t h t h e v a l u e
00_0000_1000b. This value (8), when multiplied by 4 Mbytes,
yields 32 Mbytes as the write allocate limit.
15
22
0
63
Reserved
WAELIM
16
Note
:
Hardware RESET initializes this MSR to all zeros.
W
A
E
1
5
M
Symbol
Description
Bits
WAELIM
Write Allocate Enable Limit
31-22
WAE15M
Write Allocate Enable 15-to-16-Mbyte 16
17
21
31
32