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Embedded AMD-K6™ Processors BIOS Design Guide
23913A/0—November 2000
Preliminary Information
Write Cycles
out-of-order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Write Handling Control Register (WHCR)
models 7 and 8
[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
models 8
[F:8], 9, and D . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Write Merge Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24–25
Write-Combining (WC) Memory . . . . . . . . . . . . . . . . . . . 30–31
WRMSR Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14, 16
L2 tag or data selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
page flush/invalidate register (PFIR) . . . . . . . . . . . . . . . . 36