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Model 7 and Model 8/[7:0] Registers
19
23913A/0—November 2000
Embedded AMD-K6™ Processors BIOS Design Guide
Preliminary Information
Write Handling Control Register (WHCR)
The Write Handling Control Register (WHCR) (see Figure 3 on
page 20) is an MSR that contains three fields — the Write
Cacheability Detection Enable (WCDE) bit, the Write Allocate
Enable Limit (WAELIM) field, and the Write Allocate Enable
15-to-16-Mbyte (WAE15M) bit. The WHCR register is MSR
C000_0082h.
AMD-K6 processors contain a split level-1 (L1) 64-Kbyte
writeback cache organized as a separate 32-Kbyte instruction
cache and a 32-Kbyte data cache with two-way set associativity.
The cache line size is 32 bytes and lines are read from memory
using an efficient pipelined burs t re ad cy cle. Further
performance gains are achieved by the implementation of a
write allocation scheme.
Write Allocation
A write allocate, if enabled, occurs when the processor has a
pending memory write cycle to a cacheable line and the line
does not currently reside in the L1 cache. For more information,
see the Implementation of Write Allocate in the K86™ Processors
Application Note, order# 21326, and the “Cache Organization”
chapter in the appropriate AMD-K6 or AMD-K6E processor
data sheet.
This section describes two programmable mechanisms used by
the processor to determine when to perform write allocate.
When either of these mechanisms indicates that a pending
write is to a cacheable area of memory, a write allocate is
performed.
B e fo re e n a b l i n g w r i t e a l l o c a t e o r c h a n g i n g m e m o ry
cacheability/writeability, the BIOS must writeback and
invalidate the internal cache by using the WBINVD instruction.
In addition, write allocate should be enabled only after
performing any memory sizing or typing algorithms.