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Model D Registers
Embedded AMD-K6™ Processors BIOS Design Guide
23913A/0—November 2000
Preliminary Information
Level-2 Cache Array Access Register (L2AAR)
Model D also provides the L2AAR register that allows for direct
access to the L2 cache and L2 tag arrays.
Note: The L2AAR register is identical to the Model 9
implementation. Some information in this section is
duplicated to account for the different L2 cache sizes in the
AMD-K6-2E+ and AMD-K6-IIIE+ processors.
The L2 cache in the AMD-K6-2E+ and AMD-K6-IIIE+ processors
is organized as shown in Figure 18:
■
Four 32-Kbyte ways (AMD-K6-2E+ processor) or four 64-
Kbyte ways (AMD-K6-IIIE+ processor)
■
Each way contains 512 (AMD-K6-2E+ processor) or 1024
(AMD-K6-IIIE+ processor) sets
■
Each set contains four 64-byte sectors (one sector in each
way)
■
Each sector contains two 32-byte cache lines
■
Each cache line contains four 8-byte octets
■
Each octet contains an upper and lower dword (4 bytes)
Each line within a sector contains its own MESI state bits, and
associated with each sector is a tag and LRU (Least Recently
Used) information.
Figure 18. L2 Cache Organization
51
2 o
r 1
024 s
et
s
Set 0
64 bytes
Way 2
Line1/MESI
Line0/MESI
Tag/LRU
64 bytes
Way 1
Line1/MESI
Line0/MESI
Tag/LRU
64 bytes
Way 0
Line1/MESI
Line0/MESI
Tag/LRU
64 bytes
Way 3
Line1/MESI
Line0/MESI
Tag/LRU
Set 1023