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List of Figures
vii
23913A/0—November 2000
Embedded AMD-K6™ Processors BIOS Design Guide
Preliminary Information
List of Figures
Figure 1.
CPUID Instruction Flow Chart . . . . . . . . . . . . . . . . . . . . . 12
Figure 2.
Extended Feature Enable Register (EFER)
(Models 7 and 8/[7:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 3.
Write Handling Control Register (WHCR)
(Models 7 and 8/[7:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 4.
SYSCALL/SYSRET Target Address Register (STAR)
(Models 8, 9, and D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 5.
Extended Feature Enable Register (EFER)
(Model 8/[F:8]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 6.
Write Handling Control Register (WHCR)
(Models 8/[F:8], 9, and D) . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 7.
UC/WC Cacheability Control Register (UWCCR)
(Models 8/[F:8], 9, and D) . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 8.
Processor State Observability Register (PSOR)
(Models 8/[F:8], 9, and Standard-Power D) . . . . . . . . . . . 34
Figure 9.
Page Flush/Invalidate Register (PFIR)
(Models 8/[F:8], 9, and D) . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 10. Extended Feature Enable Register (EFER)
(Models 9 and D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 11. L2 Cache Organization (AMD-K6™-III Processor) . . . . . 40
Figure 12. L2 Cache Sector and Line Organization . . . . . . . . . . . . . 41
Figure 13. L2 Tag or Data Location (AMD-K6™-III
Processor)—EDX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 14. L2 Data—EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 15. L2 Tag Information (AMD-K6™-III Processor)—EAX . . 43
Figure 16. LRU Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 17. Processor State Observability Register (PSOR)
(Model D Low-Power Versions) . . . . . . . . . . . . . . . . . . . . 46
Figure 18. L2 Cache Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 19. L2 Cache Sector and Line Organization
(same as Figure 12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49