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Model 9 Registers
41
23913A/0—November 2000
Embedded AMD-K6™ Processors BIOS Design Guide
Preliminary Information
Figure 12. L2 Cache Sector and Line Organization
Bit 20 of EDX (T/D) determines whether the access is to the L2
cache data or tag. Table 21 on page 42 describes the operation
that is performed based on the instruction and the T/D bit.
Figure 13. L2 Tag or Data Location (AMD-K6™
-III
Processor)—EDX
Upper Dword
Lower Dword
Octet 0
Line 1
Octet 1
Octet 2
Octet 3
Upper Dword
Lower Dword
Line 0
Sector
Reserved
0
Set
21
31
20 19
17 16
5
15
18
Way
4
3 2 1
6
Symbol
Description
Bit
Set
Selects the desired cache set
15-6
Line
Selects Line1 (1) or Line0 (0)
5
Octet
Selects one of four octets
4-3
Dword
Selects upper (1) or lower (0) dword
2
L
i
n
e
Octet
D
w
o
r
d
T
/
D
Symbol
Description
Bit
T/D
Selects Tag (1) or Data (0) access
20
Way
Selects desired cache way
17-16