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Model D Registers
45
23913A/0—November 2000
Embedded AMD-K6™ Processors BIOS Design Guide
Preliminary Information
Model D Registers
The AMD-K6-2E+ and AMD-K6-IIIE+ processors (Model D)
provide the twelve model-specific registers listed in Table 22.
The contents of ECX selects the MSR to be addressed by the
RDMSR and WRMSR instruction.
The AMD-K6-2E+ and AMD-K6-IIIE+ processors contain a split
Level-1 (L1) 64-Kbyte writeback cache organized as a separate
32-Kbyte instruction cache and a 32-Kbyte data cache with
two-way set associativity. The cache line size is 32 bytes, and
lines are read from memory using an efficient pipelined burst
read cycle. In addition, these processors also contain a 128-
Kbyte (AMD-K6-2E+ processor) or a 256-Kbyte (AMD-K6-IIIE+
processor), 4-way set associative, unified Level-2 (L2) cache.
Further performance gains are achieved by the implementation
of a write allocation scheme.
Table 22. Model-Specific Registers Supported by Model D
Register Name
Mnemonic ECX Value
Description Comments
Machine-Check Address Register
MCAR
00h
page 16
Identical on all models
Machine-Check Type Register
MCTR
01h
page 16
Identical on all models
Test Register 12
TR12
0Eh
page 16
Identical on all models
Time Stamp Counter
TSC
10h
page 16
Identical on all models
Extended Feature Enable Register
EFER
C000_0080h page 39
Adds L2 Disable bit (L2D) to Model
8/[F:8] implementation
Write Handling Control Register
WHCR
C000_0082h page 27
Identical to Model 8/[F:8]
SYSCALL/SYSRET Target Address Register STAR
C000_0081h page 22
Identical to Model 8/[7:0]
UC/WC Cacheability Control Register
UWCCR
C000_0085h page 30
Identical to Model 8/[F:8]
Processor State Observability Register
PSOR
C000_0087h
page 34
1
,
page 46
2
Notes:
1. Standard-power versions only.
2. Low-power versions only.
Standard-power implementation is
identical to Model 8/[F:8]. Low-
power implementation adds new
fields and renames BF to EBF.
Page Flush/Invalidate Register
PFIR
C000_0088h page 36
Identical to Model 8/[F:8]
Level-2 Cache Array Access Register
L2AAR
C000_0089h page 48
Identical to Model 9, but note dif-
fering L2 cache sizes on Model D.
Enhanced Power Management Register
2
EPMR
C000_0086h page 54
New for Model D. Supported on
low-power versions only.