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Model 9 Registers
Embedded AMD-K6™ Processors BIOS Design Guide
23913A/0—November 2000
Preliminary Information
Model 9 Registers
The AMD-K6-III processor (Model 9) provides the eleven model-
specific registers listed in Table 19.
The contents of ECX selects the MSR to be addressed by the
RDMSR and WRMSR instruction.
The AMD-K6-III processor contains a split Level-1 (L1)
64-Kbyte writeback cache organized as a separate 32-Kbyte
instruction cache and a 32-Kbyte data cache with two-way set
associativity. The cache line size is 32 bytes, and lines are read
from memory using an efficient pipelined burst read cycle. In
addition, the processor also contains a 256-Kbyte, 4-way set
associative, unified level-2 (L2) cache. Further performance
gains are achieved by the implementation of a write allocation
scheme.
Table 19. Model-Specific Registers Supported by Model 9
Register Name
Mnemonic
ECX Value
Description
Comments
Machine-Check Address Register
MCAR
00h
page 16
Identical on all models
Machine-Check Type Register
MCTR
01h
page 16
Identical on all models
Test Register 12
TR12
0Eh
page 16
Identical on all models
Time Stamp Counter
TSC
10h
page 16
Identical on all models
Extended Feature Enable Register
EFER
C000_0080h
page 39
Adds L2 Disable bit (L2D) to
Model 8/[F:8] implementation
Write Handling Control Register
WHCR
C000_0082h
page 27
Identical to Model 8/[F:8]
SYSCALL/SYSRET Target Address Regis-
ter
STAR
C000_0081h
page 22
Identical to Model 8/[7:0]
UC/WC Cacheability Control Register
UWCCR
C000_0085h
page 30
Identical to Model 8/[F:8]
Processor State Observability Register
PSOR
C000_0087h
page 34
Identical to Model 8/[F:8]
Page Flush/Invalidate Register
PFIR
C000_0088h
page 36
Identical to Model 8/[F:8]. The
invalidate and flush operations
affect both the L1 and L2 caches
on the AMD-K6-
III
processor.
Level-2 Cache Array Access Register
L2AAR
C000_0089h
page 40
New for Model 9