TMP92CF30
2009-06-12
92CF30-417
(a) Single packet mode
This is data sequence of single packet mode when CPU bus interface is used.
Figure 3.16.13 is receiving sequence. Figure 3.16.14 is transmitting sequence.
This chapter focuses on access to FIFO. For Data sequence with USB host refer to
chapter 5.
Endpoint 0 cannot be changed to exclusive single packet mode. Endpoints 1 to 3
can be changed between single packet and dual packet by setting Epx_SINGLE
register. Do not change packet when transferring.
Figure 3.16.13 Receiving Sequence in Single Packet Mode
IDLE
DATASET register
•
Check bit of EPx_DSET_A
SIZE register
•
Size of SIZE_A_L confirmation
•
Size of
SIZE_A_H confirmation
RD receiving data of size in relevant
endpoint
DATASET
=
1
DATASET register
•
Set bit of EPx_D SET_A
•
Assert EPx_DATASET signal
•
Clear receiving data in FIFO
•
Clear relevant bit of DATASET
register
Interrupt by EPx_FULLA
Check DATASET register
Receive valid data
DATASET
=
0
Wait receiving data
Summary of Contents for TLCS-900/H1 Series
Page 652: ...TMP92CF30 2009 06 12 92CF30 650 ...