Toshiba TLCS-900/H1 Series Manual Download Page 73

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TMP92CF30

2009-06-12

92CF30-71

3.6.1

Block Diagram

Figure 3.6.1 shows an overall block diagram for the DMAC.

Note: “n” denotes a channel number. Micro DMA has eight channels (0 to 7) and DMA has six channels (0 to 5).

Figure 3.6.1 Overall Block Diagram

DMAnV

DMAR

→

DMAC or micro DMA request

source setting

→

DMAC or micro DMA soft start

setting

DMAB

→

Micro DMA burst setting

DMASEL

→

DMAC or micro DMA select

setting

INTC (Interrupt Controller)

Interrupt REQ

DMASn

→

Micro DMA source address setting

DMADn

→

Micro DMA destination address setting

DMACn

→

Micro DMA transfer count setting

DMAMn

→

Micro DMA mode setting

CPU

HDMASn

→

DMA source address setting

HDMADn

→

DMA destination address setting

HDMACAn

→

DMA transfer count A setting

HDMAMn

→

DMA mode setting

DMAC

HDMACBn

→

DMA transfer count B setting

HDMAE

→

DMA operation enable/disable

Micro DMA REQ,
Micro DMA Channel

Micro DMA ACK,
INTTCn

Bus R

Bus AC

DMA REQ,
DMA Channel

DMA ACK,
INTDMAn

Address Bus

Data Bus

State

Address Bus

Data Bus

State

Address Bus

Data Bus

State

Address Bus

Data Bus

State

Source Memory, I/O

Destination Memory, I/O

Bus
Multiplexer

HDMATR

→

DMA maximum bus occupancy

time setting, mode setting

SDRAM Controller

Bus ACK

Bus REQ

State

Address Bus

Summary of Contents for TLCS-900/H1 Series

Page 1: ...TOSHIBA Original CMOS 32 Bit Microcontroller TLCS 900 H1 Series TMP92CF30FG Semiconductor Company ...

Page 2: ...Preface Thank you very much for making use of Toshiba microcomputer LSIs Before use this LSI refer the section Notes and Restrictions ...

Page 3: ...None 4 External memory expansion Expandable up to 2 1 Gbytes shared program data area Can simultaneously support 8 16 and 32 bit width external data buses Dynamic data bus sizing Separate bus system 5 Memory controller Chip select output 4 channels One channel in 4 channels is enabled detailed AC enable setting 6 8 bit timers 8 channels 7 16 bit timer event counter 2 channels 8 General purpose ser...

Page 4: ...arm pattern 5 kinds of interval interrupt 19 MMU Expandable up to 2 1 Gbytes 3 local area 8 bank method Independent bank for each program read data write data source and destination of DMAC Odd channel Even channel 20 Interrupts 58 interrupts 9 CPU interrupts Software interrupt instruction and illegal instruction 39 internal interrupts Seven selectable priority levels 10 external interrupts Seven ...

Page 5: ... Signed calculations 26 Standby function Three Halt modes IDLE2 programmable IDLE1 STOP Each pin status programmable for standby mode 27 Clock controller Two blocks of clock doubler PLL supplies 48 MHz for USB and 80 MHz for CPU from 10 MHz Clock gear function Selectable high frequency clock fc to fc 16 Clock for Timer fs 32 768 kHz 28 Operating voltage 2 power supplies Internal power supply 1 4 t...

Page 6: ...5 P75 R W NDR B P76 WAIT RTC MELODY ALARM OUT KEY BOARD I F PA0 to PA7 KI0 to KI7 PN0 to PN7 KO0 to KO7 PC7 KO8 PM2 ALARM MLDALM PLL NAND FLASH I F 2ch SBI I 2 Cbus SPI Controller SPDO PR1 SPDI PR0 SPCLK PR3 SPCS PR2 I 2 S I 2 S0 I2S0DO PF1 I2S0CKO PF0 I2S0WS PF2 TA0IN INT1 PC1 D D USB Controller X1D4 X1USB PX5 PC0 INT0 PC2 INT2 P71 WRLL NDRE P72 WRLU NDWE P86 CSZD CE 0 ND P87 CSXB CE 1 ND PJ5 NDA...

Page 7: ...76 WAIT P75 R W NDR B P74 EA25 P73 EA24 P72 WRLU NDWE 45 50 55 60 65 70 75 80 85 130 125 120 115 110 105 100 95 90 175 170 165 160 155 150 145 140 135 1 5 10 15 20 25 30 35 40 2 Pin Assignment and Pin Functions The assignment of input output pins for TMP92CF30 their names and functions are as follows 2 1 Pin Assignment Diagram Top View Figure 2 1 1 shows the pin assignment of the TMP92CF30 Figure ...

Page 8: ...s D8 to D15 NAND Flash write Write enable for NAND Flash P73 EA24 1 I O Output Port 73 I O port Expanded address 24 P74 EA25 1 I O Output Port 74 I O port Expanded address 25 P75 R W NDR B 1 I O Output Input Port 75 I O port Read Write High represents read or dummy cycle Low represents write cycle NAND Flash Ready 1 Busy 0 input P76 WAIT 1 I O Input Port 76 I O port Wait Signal used to request CPU...

Page 9: ...e rising falling edge X Plus Pin connected to X pin for Touch Screen I F P97 PY 1 Input Output Port 97 Input port schmitt input Y Plus Pin connected to Y pin for Touch Screen I F PA0 to PA7 KI0 to KI7 8 Input Input Port A0 to A7 Input port Key input 0 to 7 Pin used for key on wake up 0 to 7 Schmitt input with pull up resistor PC0 INT0 1 I O Input Port C0 I O port Schmitt input Interrupt request pi...

Page 10: ...Input Input Port G4 to G5 Input port Analog input pin 4 to 5 Input pin for A D converter PJ0 SDRAS SRLLB 1 Output Output Output Port J0 Output port Outputs strobe signal for SDRAM row address Data enable signal for D0 to D7 for SRAM PJ1 SDCAS SRLUB 1 Output Output Output Port J1 Output port Outputs strobe signal for SDRAM column address Data enable signal for D8 to D15 for SRAM PJ2 SDWE SRWR 1 Out...

Page 11: ...rrupt request pin with programmable rising falling edge Timer A7 output Output pin for 8 bit timer 7 Transmit data for serial 0 programmable Open drain output Transmit data for serial 1 programmable Open drain output PP4 INT6 TB0IN0 RXD0 RXD1 1 I O Input Input Input Input Port P4 I O port Schmitt input Interrupt request pin 6 Interrupt request pin with programmable rising falling edge Timer B0 inp...

Page 12: ...ip select signal for SD card PR3 SPCLK 1 I O Output Port R3 I O port Clock output pin for SD card PT0 to PT7 D24 to D31 8 I O I O Port T0 to T7 I O port Data Data bus D24 to D31 PV6 SDA 1 I O I O Port V6 I O port Send receive data at I 2 C mode PV7 SCL 1 I O I O Port V7 I O port Input output clock at I 2 C mode PX4 CLKOUT 1 Output Output Port X4 Output port Internal clock output pin PX5 X1USB X1D4...

Page 13: ...for reference voltage input to AD converter H VREFL 1 Input Pin for reference voltage input to AD converter L AVCC 1 Power supply pin for AD converter AVSS 1 GND pin for AD converter 0V DVCC3A 8 Power supply pin for peripheral I O A All DVCC3A pins should be connected to the power supply pin DVCC1A 4 Power supply pin for internal logic A All DVCC1A pins should be connected to the power supply pin ...

Page 14: ...requency Max 80 MHz Minimum Bus Cycle 1 clock access 12 5ns at 80 MHz Internal RAM 32 bit 2 1 1 1 clock access 8 bit 2 clock access INTC SDRAMC MEMC TSI PORT 16 bit 2 clock access MMU USB NDFC SPIC DMAC 32 bit 2 clock access I 2 S 32 bit 1 clock access MAC Internal I O 8 bit 5 to 6 clock access TMRA TMRB SIO RTC MLD ALM SBI CGEAR ADC WDT External memory SRAM MASKROM etc 8 16 bit 2 clock access wai...

Page 15: ...pt Level Mask Register to level 7 Clears bits RFP1 0 of the Status Register to 00 thereby selecting Register Bank 0 When the Reset is released the CPU starts executing instructions according to the Program Counter settings Sets the Program Counter PC as follows in accordance with the Reset Vector stored at address FFFF00H FFFF02H PC 7 0 data in location FFFF00H PC 15 8 data in location FFFF01H PC ...

Page 16: ...ite f SYS A23 A0 DATA IN D0 D31 D0 D31 Sampling After reset is released it is started from 1 wait read cycle High Z Sampling RESET RD WRxx SRWR 0FFFF00H DATA IN DATA OUT CS0 1 3 CS2 SRxxB SRxxB f SYS 15 5 16 5 Clock Note This is a timing chart of the 32 bit external bus start mode ...

Page 17: ...lies are stable as indicated by the heavy lines in the diagram above Note2 In the power on sequence the 3 3 V power supply rails must not be turned on before the ones of 1 5 V In the power off sequence the 3 3 V power supply rails must not be turned off after the ones of 1 5 V Figure 3 1 2 Power on Reset Timing Example 1 5V Power DVCC1A DVCC1B DVCC1C RESET AVCC DVCC3A Power should rise and stabili...

Page 18: ...AM0 pins as shown in Table 3 1 2 according to system usage Table 3 1 2 Operation Mode Setup Table Mode Setup input pin RESET AM1 AM0 Operation Mode 0 1 16 bit external bus starting 1 0 32 bit external bus starting 1 1 Test mode Prohibit to set 0 0 Test mode Prohibit to set ...

Page 19: ...ea cannot be used Note2 Do not use the 144K byte area 022000H to 045FFFH and the last 16 byte area FFFFF0H to FFFFFFH This area is reserved as internal area 000000H 002000H 16Mbyte area R R R R R8 16 R d8 16 nnn Direct area n 64Kbyte area nn Internal I O 8 Kbyte 04A000H 010000H Internal area FFFF00H FFFFFFH Vector table 256 Byte 000100H External memory F00000H F10000H Note2 046000H Internal Back U...

Page 20: ...newly added to the TMP92CF30 cannot be debugged with development tools Please use the actual device or a ROM emulator to debug the TMP92CF30 3 3 2 Internal I O Functions Deleted and Modified Deleted function The TMP92CF30 has only one I2S channel Channel 0 whereas the TMP92CZ26A CF26A has Channels 0 and 1 When using the TMP92CF30 therefore do not access the addresses where special function registe...

Page 21: ...U0 to PU7 LD16 to LD23 Port V PV0 PV1 PV2 PV3 PV4 Port W PW0 to PW7 Port X PX7 Port Z PZ0 to PZ7 3 3 4 Maximum Memory Size Accessible with the MMU Function Reduced With the deletion of the P84 CSZB and P85 CSZC pins the maximum memory size that can be expanded with the MMU function is reduced resulting in a reduced number of usable banks In the TMP92CZ26A CF26A the total expandable memory size is ...

Page 22: ...ed as shown below TMP92CZ26A CF26A monophonic data output I2S format Data is output from either right or left channel TMP92CF30 monophonic data output I2S format Identical data is output from both right and left channels If an ICE using the TMP92CF26A is used for development data is output from only one channel in monophonic mode For details see the chapter on the I2S Interface I2SnWS Right Left I...

Page 23: ...Pin Added In the TMP92CF30 a new Port PX5 function is added for outputting a clock that is 1 1 1 2 1 4 or 1 8 of the oscillation frequency of the X1 and X2 pins If an ICE using the TMP92CF26A is used for development and debugging this function cannot be used 3 3 9 SPI Controller Function Added In the TMP92CZ26A CF26A the SPI control signals are multiplexed with Port PR In the TMP92CF30 the SPI con...

Page 24: ...velopment and debugging the newly added Channel 1 cannot be debugged Modified function Each of the two SIO channels can be connected to the P90 P91 and P92 pins or the PP3 PP4 and PP5 pins However if an ICE using the TMP92CF26A is used for development and debugging this modified port switching function cannot be debugged fIO SCLK0 input φT0 Internal Data Bus SCLK0 output RXD0 input TXD0 CTS0 fIO S...

Page 25: ...y Type Interrupt Source Micro DMA Request Source Vector Value Vector Reference Address Micro DMA HDMA Start Vector 1 Reset or SWI0 instruction 0000H FFFF00H 2 SWI1 instruction 0004H FFFF04H Omitted Omitted 40 INTI2S0 I 2 S Channel 0 009CH FFFF9CH 27H 41 Reserved 42 INTADM AD monitor function 00A4H FFFFA4H 29H 43 INTSBI SBI 00A8H FFFFA8H 2AH 44 INTSPIRX SPIC receive 00ACH FFFFACH 2BH 45 INTSPITX SP...

Page 26: ...C Deleted General purpose port pins PV0 PV1 PV2 PV3 PV4 PX7 PW0 to PW7 Deleted Deleted Deleted Deleted Deleted Deleted Deleted 15 port pins are deleted 16 Power supply pins DVCC3A 12 DVCC3B 1 DVCC1A 5 DVCC1B 1 DVCC1C 1 DVCC1S 1 DVSSCOM 12 DVCC3A 8 DVCC3B 0 DVCC1A 4 DVCC1B 1 DVCC1C 1 DVCC1S 1 DVSSCOM 8 10 power supply pins deleted 10 Dummy 4 pins None 4 dummy pins are deleted 4 NMI Not supports Add...

Page 27: ... clock doubler PLL 3 standby controller and 4 noise reduction circuits They are used for low power low noise systems This chapter is organized as follows 3 4 1 Block diagram of system clock 3 4 2 SFR 3 4 3 System clock controller 3 4 4 Clock doubler PLL 3 4 5 Noise reduction circuits 3 4 6 Standby controller ...

Page 28: ...r instruction instruction interrupt interrupt instruction instruction interrupt interrupt instruction instruction interrupt interrupt instruction interrupt STOP mode Stops all circuits Instruction Note Note 1 When shifting from PLL ON mode to PLL OFF mode execute the following setting in the same order 1 Change CPU clock Set 0 to PLLCR0 FCSEL 2 Stop PLL circuit Set 0 to PLLCR1 PLLON Note 2 It is n...

Page 29: ...YSCR1 GEAR2 0 2 fSYS 2 φT0TMR fs φT0 High frequency Oscillator circuit 8 2 fIO Lock up timer PLL PLLCR1 PLLON PLLCR0 LUPFG 8 Clock Doubler1 PLL1 24 fUSB SYSCR0 USBCLK1 0 5 fPLLUSB X1USB TMRA0 7 TMRB0 1 fSYS CPU RAM Interrupt Controller I O ports Prescaler φT0TMR SIO0 RTC fs Prescaler MLD ALM SDRAMC fio Memory Controller NAND Flash Controller I 2 S TSI SPIC SBI Prescaler DMAC MAC fUSB USB ADC 2 fPL...

Page 30: ... range of input frequency is 6 to 10MHz Don t input the clock over 10MHz Table 3 4 1 Setting example for fOSCH High frequency fOSCH System clock fSYS System clock fSYS USB clock fUSB a USB in use with PLL PLL0 ON PLL1 ON 10 0 MHz Max 80 MHz Max 60 MHz 48 MHz b USB not in use with PLL PLL0 ON PLL1 OFF Max 10 0 MHz Max 80 MHz Max 60 MHz c USB not in use without PLL PLL0 OFF PLL1 OFF Max 10 0 MHz Max...

Page 31: ...erved 110 Reserved 111 Reserved SYSCR1 10E1H 7 6 5 4 3 2 1 0 bit Symbol CKOSEL WUPTM1 WUPTM0 HALTM1 HALTM0 Read write R W Reset State 0 0 1 0 1 1 SYSCR2 10E2H Function Always write 0 Select CLKOUT 0 fSYS 1 fS Warm Up Timer 00 Reserved 01 28 inputted frequency 10 214 inputted frequency 11 216 inputted frequency HALT mode 00 Reserved 01 STOP mode 10 IDLE1 mode 11 IDLE2 mode Note1 The unassigned regi...

Page 32: ...ead Write Reset State EMCCR1 10E4H Function Bit symbol Read Write Reset State EMCCR2 10E5H Function Switch the protect ON OFF by writing the following to 1 st KEY 2 nd KEY 1 st KEY write in sequence EMCCR1 5AH EMCCR2 A5H 2 nd KEY write in sequence EMCCR1 A5H EMCCR2 5AH Note1 When restarting the oscillator in the stop oscillation state e g Restarting the oscillator in STOP mode set EMCCR0 DRVOSCH D...

Page 33: ... R W System Reset State 1 1 1 1 1 1 1 1 Hot Reset State PxDR xxxxH Function Output Input buffer drive register for standby mode Purpose and using This register is used to set each pin status at stand by mode All ports have registers of the format shown above x indicates the port name For each register refer to 3 7 Function of Ports Before HALT instruction is executed set each register pin status T...

Page 34: ...er SYSCR1 GEAR2 0 to either fc fc 2 fc 4 fc 8 or fc 16 Using the clock gear to select a lower value of fSYS reduces power consumption Example Changing clock gear SYSCR1 EQU 10E1H LD SYSCR1 XXXXX001B Changes system clock fSYS to fc 2 LD DUMMY 00H Dummy instruction X don t care High speed clock gear changing To change the clock gear write the register value to the SYSCR1 GEAR2 0 register It is neces...

Page 35: ...0MHz measured by 13 stage binary counter Note1 Input frequency range for PLL The input frequency range High frequency oscillation for PLL is as follows fOSCH X to X MHz Vcc 1 4 to 1 6V Note2 PLLCR0 LUPFG The logic of PLLCR0 LUPFG is different from 900 L1 s DFM Exercise care in determining theend of lock up time Note3 PLLCR1 PLL0 PLLCR1 PLL1 It is not possible to turn ON both PLL0 and PLL1 simultan...

Page 36: ...c from 10 MHz to 60 MHz X Don t care Counts up by fOSCH During lock up PLL0 PLL output fPLL Lockup timer LUPFG System clock fSYS Starts PLL0 operation and Starts lock up Ends of lock up Changes from 10MHz to 60MHz After lock up FCSEL Example 2 PLL0 stopping PLLCR0 EQU 10E8H PLLCR1 EQU 10E9H LD PLLCR0 X0XXXXXXB Changes fc from 60 MHz to10 MHz LD PLLCR1 0XXXXXXXB Stop PLL X Don t care PLL0 PLL0 outp...

Page 37: ... up lock up start LUP BIT 5 PLLCR0 JR Z LUP Check for lock up end flag LD PLLCR0 X1XXXXXXB Change the system clock fOSCH to fPLL X Don t care 2 Change Stop Control OK PLL0 use mode fPLL High frequency oscillator operation mode fOSCH PLL0 Stop LD PLLCR0 X0XXXXXXB Change the system clock fPLL to fOSCH LD PLLCR1 0XXXXXXXB Stop PLL0 X Don t care OK PLL0 use mode fPLL Set the STOP mode High frequency o...

Page 38: ... register These are set in EMCCR0 to EMCCR2 registers 1 Reduced drivability for high frequency oscillator circuit Purpose Reduces noise and power for oscillator when a resonator is used Clock diagram Setting method The drivability of the oscillator is reduced by writing 0 to EMCCR0 DRVOSCH register At reset DRVOSCH is initialized to 1 and the oscillator starts oscillation by normal drivability whe...

Page 39: ...quency oscillator circuit Purpose Remove the need for twin drives and protect prevent operational errors caused by noise input to X2 pin when an external oscillator is used Block diagram Setting method The oscillator is disabled and starts operation as buffer by writing 1 to EMCCR0 EXTIN register X2 pin s output is always 1 At reset EXTIN is initialized to 0 Note Do not write EMCCR0 EXTIN 1 when u...

Page 40: ...MAMR2 MAMR3 PMEMCR MEMCR0 CSTMGCR WRTMGCR RDTMGCR0 RDTMGCR1 BROMCR 2 MMU LOCALPX PY PZ LOCALLX LY LZ LOCALRX RY RZ LOCALWX WY WZ LOCALESX ESY ESZ LOCALEDX EDY EDZ LOCALOSX OSY OSZ LOCALODX ODY ODZ 3 Clock gear SYSCR0 SYSCR1 SYSCR2 EMCCR0 4 PLL PLLCR0 PLLCR1 Operation explanation Execute and release of protection write operation to specified SFR becomes possible by setting up a double key to EMCCR1...

Page 41: ...the CPU has executed the HALT instruction This is the case regardless of stand by mode IDLE2 IDLE1 or STOP The Output Input buffer control table is shown below OE PxnD Output buffer Input buffer 0 0 OFF OFF 0 1 OFF ON 1 0 OFF OFF 1 1 ON OFF Note1 OE denotes an output enable signal before stand by mode Basically PxCR is used as OE Note2 n in PxnD denotes the bit number of PORTx The subsequent actio...

Page 42: ... status executing the instruction that follows the HALT instruction When the interrupt request level set before executing the HALT instruction is less than the value of the interrupt mask register HALT mode release is not executed in non maskable interrupts interrupt processing is processed after releasing the halt mode regardless of the value of the mask register However only for NMI INT0 to INT5...

Page 43: ... instruction Cannot be used to release the halt mode The priority level interrupt request level of non maskable interrupts is fixed to 7 the highest priority level This combination is not available 1 Release of the HALT mode is executed after warm up time has elapsed 2 6 interrupts of all 24 INTUSB sources can release Halt state from IDLE1 mode allowing for the construction of low power dissipatio...

Page 44: ...DLE1 Mode Address 8200H LD PCFC 02H Sets PC1 to INT0 interrupt 8203H LD IIMC0 00H Select INT0 interrupt rising edge 8206H LD INTE0 06H Sets INT0 interrupt level to 6 8209H EI 5 Sets CPU interrupt level to 5 820BH LD SYSCR2 28H Sets Halt mode to IDLE1 mode 820EH HALT Halts CPU INT0 INT0 interrupt routine RETI 820FH LD XX XX ...

Page 45: ... Mode In IDLE1 Mode only the internal oscillator and the RTC and MLD continue to operate The system clock stops In the Halt state the interrupt request is sampled asynchronously with the system clock however clearance of the Halt state i e restart of operation is synchronous with it Figure 3 4 8 illustrates the timing for clearance of the IDLE1 Mode Halt state by an interrupt Figure 3 4 8 Timing c...

Page 46: ...er to allow oscillation to stabilize Figure 3 4 9 illustrates the timing for clearance of the STOP Mode Halt state by an interrupt Figure 3 4 9 Timing chart for STOP Mode Halt state cleared by interrupt Table 3 4 6 Example of warming up time after releasing STOP mode at fOSCH 10 MHz SYSCR2 WUPTM1 0 01 28 10 214 11 216 25 6 μs 1 6384 ms 6 5536 ms Interrupt for releasing Halt Data Data STOP mode War...

Page 47: ...2IN ON ON OFF PC4 PC7 PF0 PF2 ON ON ON PG0 PG2 PG4 PG5 2 PG3 2 ADTRG OFF ON ON upon port read ON OFF ON PJ5 PJ6 ON PL0 PL7 D16 D23 16 bit external bus starting ON 16 bit external bus starting OFF ON upon external read OFF OFF PN0 PN7 PP3 INT5 PP4 INT6 TB0IN0 PP5 INT7 TB1IN0 PR0 SPDI ON ON OFF PR1 PR3 ON PT0 PT7 D24 D31 16 bit external bus starting ON 16 bit external bus starting OFF ON upon extern...

Page 48: ...N OFF ON P40 P47 A0 A7 P50 P57 A8 A15 ON P60 67 A16 A23 ON P70 RD ON P71 WRLL NDRE P72 WRLU NDWE P73 EA24 P74 EA25 P75 R W ON ON OFF P76 OFF P80 0 CS P81 1 CS SDCS P82 2 CS CSZA SDCS P83 3 CS CSXA P84 CSZB P85 CSZC P86 CSZD CE 0 ND P87 CSXB CE 1 ND ON P90 TXD0 ON ON OFF P91 P92 SCLK0 OFF ON ON OFF P96 PX P97 PY ON ON OFF PC0 PC3 PC4 EA26 PC5 EA27 PC6 EA28 PC7 KO8 PF0 I2S0CKO PF1 I2S0DO PF2 I2S0WS ...

Page 49: ...LM TA1OUT PM2 MLDALM ALARM PM7 ON PN0 PN7 KO0 KO7 PP3 TA7OUT ON ON OFF PP4 PP5 OFF PP6 TB0OUT0 PP7 TB1OUT0 ON ON ON OFF PR0 PR1 SPDO PR2 SPCS PR3 SPCLK PT0 PT7 D24 D31 OFF ON ON OFF PV6 SDA PV7 SCL OFF ON ON OFF PX4 CLKOUT ON ON ON OFF PX5 OFF ON ON OFF D D OFF ON OF depend on USBC operation X2 IDLE2 1 ON STOP output H XT2 Always ON IDLE2 1 ON STOP output HZ ON The buffer is always turned on When ...

Page 50: ...greater than or equal to the value in the interrupt mask register the CPU accepts the interrupt However software interrupts and illegal instruction interrupts generated by the CPU and are processed irrespective of the value in IFF2 0 The value in the interrupt mask register IFF2 0 can be changed using the EI instruction EI num sets IFF2 0 to num For example the command EI3 enables the acceptance o...

Page 51: ...cepted interrupt 1 INTNEST INTNEST 1 PC FFFF00H V Interrupt processing program RETI instruction POP SR POP PC INTNEST INTNEST 1 End Clear interrupt request flag YES NO Data transfer by micro DMA COUNT COUNT 1 COUNT 0 NO Clear vector register generating micro DMA transfer end interrupt INTTC0 YES Micro DMA processing General purpose interrupt processing DMA soft start request Start specified by HDM...

Page 52: ...tack and decrements the interrupt nesting counter INTNEST by 1 Non maskable interrupts cannot be disabled by a user program Maskable interrupts however can be enabled or disabled by a user program A program can set the priority level for each interrupt source A priority level setting of 0 or 7 will disable an interrupt request If an interrupt request is received for an interrupt with a priority le...

Page 53: ... 13H 21 INTP0 Protect 0 Write to SFR 0050H FFFF50H 14H 22 Reserved 0054H FFFF54H 15H 23 INTTA0 0 0058H FFFF58H 16H 24 INTTA1 8 bit timer 1 005CH FFFF5CH 17H 25 INTTA2 8 bit timer 2 0060H FFFF60H 18H 26 INTTA3 8 bit timer 3 0064H FFFF64H 19H 27 INTTB0 16 bit timer 0 0068H FFFF68H 1AH 28 INTTB1 16 bit timer 0 006CH FFFF6CH 1BH 29 INTKEY Key wakeup 0070H FFFF70H 1CH 30 INTRTC RTC Alarm interrupt 0074...

Page 54: ...A1 HDMA1 end 00D4H FFFFD4H 35H 55 INTTC2 INTDMA2 Micro DMA2 HDMA2 end 00D8H FFFFD8H 36H 56 INTTC3 INTDMA3 Micro DMA3 HDMA3 end 00DCH FFFFDCH 37H 57 INTTC4 INTDMA4 Micro DMA4 HDMA4 end 00E0H FFFFE0H 38H 58 INTTC5 INTDMA5 Micro DMA5 HDMA5 end 00E4H FFFFE4H 39H 59 INTTC6 Micro DMA6 end 00E8H FFFFE8H 3AH 60 INTTC7 Micro DMA7 end 00ECH FFFFECH 3BH to Maskable Reserved 00F0H 00FCH FFFFF0H FFFFFCH to Not...

Page 55: ... performed at the highest priority level for maskable interrupts Level 6 regardless of the priority level of the interrupt source Because the micro DMA function is implemented through the CPU when the CPU is placed in a stand by state IDLE2 IDLE1 STOP by a HALT instruction the requirement of the micro DMA will be ignored Pending Micro DMA supports 8 channels and can be transferred continuously by ...

Page 56: ...et Therefore if the interrupt is only being used to initiate micro DMA HDMA and not as a general purpose interrupt the interrupt level should first be set to 0 i e interrupt requests should be disabled If micro DMA and general purpose interrupts are being used together as described above the level of the interrupt which is being used to initiate micro DMA processing should first be set to a lower ...

Page 57: ...counter up to 65536 micro DMA processing operations can be performed per interrupt source Provided that the transfer counter for the source is initially set to 0000H Micro DMA processing can be initiated by any one of 47 different interrupts the 46 interrupts shown in the micro DMA start vectors in Table 3 5 1 and a micro DMA soft start Figure 3 5 2 shows a 2 byte transfer carried out using a micr...

Page 58: ...er by interrupt source micro DMA transfer counter doesn t change Don t use Read modify write instruction to avoid writign to other bits by mistake Note1 If it is started by software don t set any channels to start in same time Note2 If be started sequentially restart it after confirming micro DMA of all channels is completed all micro DMA are set to 0 Symbol Name Address 7 6 5 4 3 2 1 0 DREQ7 DREQ...

Page 59: ...urce and destination DEC mode DMADn DMASn DMACn DMACn 1 If DMACn 0 then INTTCn 6 states 1 1 0 z z Destination and fixed mode DMADn DMASn DMACn DMACn 1 If DMACn 0 then INTTCn 5 states 1 1 1 00 Counter mode DMASn DMASn 1 DMACn DMACn 1 If DMACn 0 then INTTCn 5 states ZZ 00 1 byte transfer 01 2 byte transfer 10 4 byte transfer 11 Reserved Note 1 n stands for the micro DMA channel number 0 to 7 DMADn D...

Page 60: ...iority or in other words the interrupt with the lowest vector value is used to determine which interrupt request is accepted first The 3rd and 7th bits of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has occurred If several interrupts are generated simultaneously the interrupt controller sends the...

Page 61: ... 44H D Q CLR Y1 Y2 Y3 Y4 Y5 Y6 A B C Dn Dn 1 Dn 2 Interrupt request F F Interrupt vector read Micro DMA acknowledge Interrupt request F F Dn 3 A B C Interrupt vector read D2 D3 D4 D5 D6 D7 Selector S Q R 0 1 2 7 A B C D0 D1 Interrupt vector read Interrupt mask F F Micro DMA request HALT release INTRQ2 0 IFF 2 0 then 1 INTRQ2 to 0 IFF2 to 0 Interrupt mask detect RESET EI 1 to 7 DI Interrupt request...

Page 62: ...W R R W INTETA01 INTTA0 INTTA1 enable D4H 0 0 0 0 0 0 0 0 INTTA3 TMRA3 INTTA2 TMRA2 ITA3C ITA3M2 ITA3M1 ITA3M0 ITA2C ITA2M2 ITA2M1 ITA2M0 R R W R R W INTETA23 INTTA2 INTTA3 enable D5H 0 0 0 0 0 0 0 0 INTTA5 TMRA5 INTTA4 TMRA4 ITA5C ITA5M2 ITA5M1 ITA5M0 ITA4C ITA4M2 ITA4M1 ITA4M0 R R W R R W INTETA45 INTTA4 INTTA5 enable D6H 0 0 0 0 0 0 0 0 INTTA7 TMRA7 INTTA6 TMRA6 ITA7C ITA7M2 ITA7M1 ITA7M0 ITA6C...

Page 63: ...1 IADMM0 ISBI0C ISBIM2 ISBIM1 ISBIM0 R R W R R W INTESBIADM INTSBI INTADM enable E0H 0 0 0 0 0 0 0 0 INTSPITX INTSPIRX ISPITC ISPITM2 ISPITM1 ISPITM0 ISPIRC ISPIRM2 ISPIRM1 ISPIRM0 R R W R R W INTESPI INTSPI enable E1H 0 0 0 0 0 0 0 0 INTUSB IUSBC IUSBM2 IUSBM1 IUSBM0 R R W INTEUSB INTUSB enable E3H Always write 0 0 0 0 0 INTALM IALMC IALMM2 IALMM1 IALMM0 R R W INTEALM INTALM enable E5H Always wri...

Page 64: ...NTP0 IP0C IP0M2 IP0M1 IP0M0 R R W INTEP0 INTP0 enable EEH Always write 0 0 0 0 INTADHP INTAD IADHPC IADHPM2 IADHPM1 IADHPM0 IADC IADM2 IADM1 IADM0 R R W R W R W 0INTEAD INTAD INTADHP enable EFH 0 0 0 0 0 0 0 0 lxxM2 lxxM1 lxxM0 Function Write 0 0 0 Disables interrupt requests 0 0 1 Sets interrupt priority level to 1 0 1 0 Sets interrupt priority level to 2 0 1 1 Sets interrupt priority level to 3 ...

Page 65: ...DMA5C ITC5M2 IDMA5M2 ITC5M1 IDMA5M1 ITC5M0 IDMA5M0 ITC4C IDMA4C ITC4M2 IDMA4M2 ITC4M1 IDMA4M1 ITC4M0 IDMA4M0 R R W R R W INTETC45 INTEDMA45 INTTC4 INTDMA4 INTTC5 INTDMA5 enable F3H 0 0 0 0 0 0 0 0 INTTC7 DMA7 INTTC6 DMA6 ITC7C ITC7M2 ITC7M1 ITC7M0 ITC6C ITC6M2 ITC6M1 ITC6M0 R R W R R W INTETC67 INTTC6 INTTC7 enable F4H 0 0 0 0 0 0 0 0 NMI INTWD ITCNMI ITCWD R R INTWDT NMI INTWD NMI Flag enable F7H...

Page 66: ...LD INTCLR 0AH Clears interrupt request flag NOP Wait EI execution NOP NOP EI X Don t care No change Note 2 See electrical characteristics in section 4 for external interrupt input pulse width Note 3 In port setting if 16 bit timer input is selected and capture control is executed INT6 and INT7 don t depend on IIMC1 register setting INT6 and INT7 operate by setting TBnMOD TBnCPM1 0 Settings of Exte...

Page 67: ...end interrupt always write 1 INTRX edge enable 0 Edge detect INTRX 1 H level INTRX Symbol Name Address 7 6 5 4 3 2 1 0 IR1LE IR0LE W W 0 0 1 1 SIMC SIO interrupt mode control F5H Prohibit RMW Always write 0 Note Always write 0 0 INTRX1 edge mode 1 INTRX1 level mode 0 INTRX0 edge mode 1 INTRX0 level mode ...

Page 68: ...MACn or HDMA transfer counter B HDMACBn value reaches 0 the micro DMA HDMA transfer end interrupt corresponding to the channel is sent to the interrupt controller the micro DMA HDMA start vector register is cleared and the micro DMA HDMA start source for the channel is cleared Therefore in order for micro DMA HDMA processing to continue the micro DMA HDMA start vector register must be set again du...

Page 69: ...0 R W 0 0 0 0 0 0 DMA5V DMA5 start vector 105H DMA5 start vector DMA6V5 DMA6V4 DMA6V3 DMA6V2 DMA6V1 DMA6V0 R W 0 0 0 0 0 0 DMA6V DMA6 start vector 106H DMA6 start vector DMA7V5 DMA7V4 DMA7V3 DMA7V2 DMA7V1 DMA7V0 R W 0 0 0 0 0 0 DMA7V DMA7 start vector 107H DMA7 start vector 6 Micro DMA HDMA select register This register selectable that is started either Micro DMA or HDMA processing Micro DMA HDMA ...

Page 70: ...n the transfer counter register reaches 0 Setting any of the bits in the register DMAB which correspond to a micro DMA channel as shown below to 1 specifies that any micro DMA transfer on that channel will be a burst transfer Symbol Name Address 7 6 5 4 3 2 1 0 DBST7 DBST6 DBST5 DBST4 DBST3 DBST2 DBST1 DBST0 R W 0 0 0 0 0 0 0 0 DMAB DMA burst 108H 1 DMA request on Burst mode ...

Page 71: ...eral interrupt request passes through the S input of the flip flop and becomes the Q output If the interrupt input mode is changed from edge mode to level mode the interrupt request flag is cleared automatically If the CPU enters the interrupt response sequence as a result of INT0 going from 0 to 1 INT0 must then be held at 1 until the interrupt response sequence has been completed If INT0 is set ...

Page 72: ...d DMA end interrupt Two count registers are provided to execute multiple DMA transfers by one DMA request and to generate multiple DMA requests at a time The DMA end interrupt INTDMA0 to INTDMA5 is also provided so that a general purpose interrupt routine can be used to prepare for the next processing 6 Priorities among DMA channels the same as the micro DMA acceptance specifications of the INTC D...

Page 73: ...tination address setting DMACn Micro DMA transfer count setting 15 0 DMAMn Micro DMA mode setting 7 0 CPU HDMASn DMA source address setting 31 0 HDMADn DMA destination address setting HDMACAn DMA transfer count A setting 15 0 HDMAMn DMA mode setting 7 0 DMAC HDMACBn DMA transfer count B setting HDMAE DMA operation enable disable Micro DMA REQ Micro DMA Channel Micro DMA ACK INTTCn Bus REQ Bus ACK ...

Page 74: ...Symbol DnSA7 DnSA6 DnSA5 DnSA4 DnSA3 DnSA2 DnSA1 DnSA0 Read Write R W Reset State 0 0 0 0 0 0 0 0 Function Source address 7 0 for DMAn HDMASn 15 14 13 12 11 10 9 8 bit Symbol DnSA15 DnSA14 DnSA13 DnSA12 DnSA11 DnSA10 DnSA9 DnSA8 Read Write R W Reset State 0 0 0 0 0 0 0 0 Function Source address 15 8 for DMAn 23 22 21 20 19 18 17 16 bit Symbol DnSA23 DnSA22 DnSA21 DnSA20 DnSA19 DnSA18 DnSA17 DnSA16...

Page 75: ...Write R W Reset State 0 0 0 0 0 0 0 0 Function Destination address 7 0 for DMAn 15 14 13 12 11 10 9 8 bit Symbol DnDA15 DnDA14 DnDA13 DnDA12 DnDA11 DnDA10 DnDA9 DnDA8 Read Write R W Reset State 0 0 0 0 0 0 0 0 Function Destination address 15 8 for DMAn 23 22 21 20 19 18 17 16 bit Symbol DnDA23 DnDA22 DnDA21 DnDA20 DnDA19 DnDA18 DnDA17 DnDA16 Read Write R W Reset State 0 0 0 0 0 0 0 0 HDMADn Functi...

Page 76: ...r 7 6 5 4 3 2 1 0 bit Symbol DnCA7 DnCA6 DnCA5 DnCA4 DnCA3 DnCA2 DnCA1 DnCA0 Read Write R W Reset State 0 0 0 0 0 0 0 0 Function Transfer count A 7 0 for DMAn 15 14 13 12 11 10 9 8 bit Symbol DnCA15 DnCA14 DnCA13 DnCA12 DnCA11 DnCA10 DnCA9 DnCA8 Read Write R W Reset State 0 0 0 0 0 0 0 0 HDMACAn Function Transfer count A 15 8 for DMAn Transfer count A 15 8 Transfer count A 7 0 Channel 0 0909H HDMA...

Page 77: ...0 bit Symbol DnCB7 DnCB6 DnCB5 DnCB4 DnCB3 DnCB2 DnCB1 DnCB0 Read Write R W Reset State 0 0 0 0 0 0 0 0 Function Transfer count B 7 0 for DMAn 15 14 13 12 11 10 9 8 bit Symbol DnCB15 DnCB14 DnCB13 DnCB12 DnCB11 DnCB10 DnCB9 DnCB8 Read Write R W Reset State 0 0 0 0 0 0 0 0 HDMACBn Function Transfer count B 15 8 for DMAn Transfer count B 15 8 Transfer count B 7 0 Channel 0 090BH HDMACB0 090AH Channe...

Page 78: ... O 011 Source DEC MEM I O 100 Source destination INC MEM MEM 101 Source destination DEC MEM MEM 110 Source destination fixed I O I O 111 Reserved Note 2 Transfer data size 00 1 byte 01 2 bytes 10 4 bytes 11 Reserved Transfer mode 7 0 Channel 0 HDMAM0 090CH Channel 1 HDMAM1 091CH Channel 2 HDMAM2 092CH Channel 3 HDMAM3 093CH Channel 4 HDMAM4 094CH Channel 5 HDMAM5 095CH Note 1 Read modify write ins...

Page 79: ...When the DMAC occupies the bus for the duration of time set in this register it releases the bus even if the specified DMA operation has not been completed yet After waiting for 16 states the DMAC asserts a bus request again to execute the rest of the DMA operation The DMAC counts the bus occupancy time regardless of which channel is occupying the bus To set the maximum bus occupancy time ensure t...

Page 80: ...quested Figure 3 6 9 Overall Flowchart Interrupt specified by DMA start vector Yes No Bus ACK No Yes HDMASn read HDMADn write Timer match No Yes HDMACAn 1 0 No Yes Bus REQ deassert Internal timer start HDMACBn 1 0 Yes No INTDMAn assert END Interrupt request F F clear bus REQ assert To general purpose interrupt or micro DMA processing flow Interrupt DMA request ...

Page 81: ... logical addresses The DMAC accesses the specified source and destination addresses according to the bus width and number of waits set in the memory controller and the bank settings made in the MMU Although the bus sizing function is supported the address alignment function is not supported Therefore specify an even numbered address for transferring 2 bytes and an address that is an integral multi...

Page 82: ...r 32 Kbytes have been transferred the INTDMA0 interrupt routine shall be activated to prepare for the next processing a Main routine No Instruction Comments 1 ldl hdmas0 2000H Source address 2000H 2 ldl hdmad0 i2sbuf Destination address i2sbuf 3 ldw hdmaca0 16 Counter A 16 4 ldw hdmacb0 512 Counter B 512 32768 64 5 ldb hdmam0 0AH Transfer mode source INC 4 bytes 6 set 0 hdmae Enable DMA channel 0 ...

Page 83: ...mission start is to set to 1 DMAR register However DMAR register can t be used to confirm flag of transmission end DMAR register reset to 0 when HDMA release bus occupation once with HDMATR function We recommend to use HDMACBn register counter value to confirm flag of transmission end ...

Page 84: ...tSTOP HDMA based on the transfer time transfer start interval and number of channels to be used CPU bus stop rate tSTOP HDMA s HDMA start interval s HDMA start interval s HDMA start interrupt period s Note The HDMA start interval depends on the period of the HDMA start interrupt source However it is also possible to start HDMA by software tSTOP HDMA s Source read time Destination write time Transf...

Page 85: ...n 4 byte units the transfer count is calculated as follows 5 Kbytes 4 bytes 1280 times Since I2S generates an interrupt for every 64 bytes the DMAC s counter A is set to 16 64 bytes 4 bytes 16 times and counter B is set to 80 Note Since an interrupt is generated 80 times the first read to internal RAM which requires 1 additional state occurs 80 times requiring additional 80 states in total In addi...

Page 86: ...I O bit WRLU NDWE P73 1 I O bit EA24 P74 1 I O bit EA25 P75 1 I O bit R W NDR B Port 7 P76 1 I O bit WAIT P80 1 Output Fixed 0 CS P81 1 Output Fixed 1 CS SDCS P82 1 Output Fixed 2 CS CSZA SDCS P83 1 Output Fixed 3 CS CSXA P86 1 Output Fixed CSZD CE 0 ND Port 8 P87 1 Output Fixed CSXB CE 1 ND P90 1 I O bit TXD0 TXD1 P91 1 I O bit RXD0 RXD1 P92 1 I O bit SCLK0 0 CTS SCLK1 1 CTS P96 1 Input PD Fixed ...

Page 87: ...ort K PK0 PK7 8 Output Fixed Port L PL0 to PL7 8 I O bit D16 to D23 PM1 1 Output Fixed MLDALM TA1OUT PM2 1 Output Fixed ALARM MLDALM Port M PM7 1 Output Fixed Port N PN0 to PN7 8 I O bit KO0 to KO7 PP3 1 I O bit INT5 TA7OUT TXD0 TXD1 PP4 1 I O bit INT6 TB0IN0 RXD0 RXD1 PP5 1 I O bit INT7 TB1IN0 SCLK0 0 CTS SCLK1 1 CTS Port P PP6 1 Output Fixed TB0OUT0 PR0 1 I O bit SPDI PR1 1 I O bit SPDO PR2 1 I ...

Page 88: ... 6 P60 to P67 A16 to A23 Output X X 1 None P70 to P76 Output port X 1 0 P71 to P76 Input port X 0 0 P70 RD Output X None 1 WRLL Output 1 P71 NDRE Output 0 1 1 WRLU Output 1 P72 NDWE Output 0 1 1 P73 EA24 Output X 1 1 P74 EA25 Output X 1 1 R W Output X 1 1 P75 NDR B Input X 0 1 Port 7 P76 WAIT Input X 0 1 None P80 to P87 Output port X 0 0 P80 0 CS Output X 1 None 1 CS Output X 1 0 P81 SDCS Output X...

Page 89: ...None 1 None Input port X 0 None Port A PA0 to PA7 KI0 to KI7 Input X None 1 None Input port X 0 0 None PC0 to PC3 PC5 to PC7 Output port X 1 0 None Input port X 0 0 X PC4 Output port X 1 0 X PC0 INT0 Input X 0 1 None INT1 Input X 0 1 None PC1 TA0IN Input X 1 1 None PC2 INT2 Input X 0 1 None INT3 Input X 0 1 None PC3 TA2IN Input X 1 1 None EA26 Output X 0 1 X PC4 SPDI Input X 1 1 1 PC4 PR0 SPDI Inp...

Page 90: ...S SRLUB Output X 1 PJ2 SDWE SRWR Output X 1 PJ3 SDLLDQM Output X 1 PJ4 SDLUDQM Output X None 1 PJ5 NDALE Output X 1 1 PJ5 SRUUB output X 0 1 PJ6 NDCLE Output X 1 1 PJ6 SRULB output X 0 1 Port J PJ7 SDCKE Output X None 1 None Port K PK0 to PK7 Output port X None 0 None Input port X 0 0 0 Output port X 1 0 0 Port L PL0 to PL7 D16 to D23 X X X 1 PM1 PM2 PM7 Output port X 0 TA1OUTOutput 0 1 PM1 MLDALM...

Page 91: ...put X X X PP2F2 1 PP5F2 0 PP6 RXD1 P91 RXD1 Input X X X PP2F2 1 PP5F2 1 INT7 Input X 0 1 PP3F2 0 TB1IN0 Input X 1 1 PP3F2 0 SCLK1 PP5 SCLK1 Input 1 CTS Input X 0 X PP3F2 1 PP6F2 0 SCLK1 P92 SCLK1 Input 1 CTS Input X 0 X PP3F2 1 PP6F2 1 SCLK0 Output X 1 X PP3F2 1 PP6F2 1 PP5 SCLK1 Output X 1 X PP3F2 1 PP6F2 0 Port P PP7 TB1OUT0 Output X None 1 None Input port X 0 0 PR0 to PR3 Output port X 1 0 PR0 ...

Page 92: ...PnFC PnFC2 PX5 Input port X 0 0 X PX4 Output port X None 0 X PX5 Output port X 1 0 X PX4 CLKOUT Output 0 None 1 X X1USB Input X 0 1 None X1D4 Output Output clock 1 8 1 1 1 PX5F2 4F2 00 X1D4 Output Output clock 1 4 1 1 1 PX5F2 4F2 01 X1D4 Output Output clock 1 2 1 1 1 PX5F2 4F2 10 Port X PX5 X1D4 Output Output clock 1 1 1 1 1 PX5F2 4F2 11 ...

Page 93: ...ction as a data bus D8 to D15 Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 1 to the following function pins AM1 AM0 Function Setting after reset is released 0 0 1 1 0 1 0 1 Don t use this setting Data bus D8 to D15 Data bus D8 to D15 Don t use this setting Figure 3 7 1 Port1 P1CR Register P1FC Register P1 Register S 0 1 Selector S 1 0 Selector External write...

Page 94: ...stem Reset State 0 0 0 0 0 0 0 0 P1CR 0006H Function 0 Input 1 Output Port 1 Function register 7 6 5 4 3 2 1 0 bit Symbol P1F Read Write W System Reset State 1 P1FC 0007H Function 0 Port 1 Data bus D8 to D15 Port 1 Drive register 7 6 5 4 3 2 1 0 bit Symbol P17D P16D P15D P14D P13D P12D P11D P10D Read Write R W System Reset State 1 1 1 1 1 1 1 1 P1DR 0081H Function Input Output buffer drive registe...

Page 95: ...Each bit can be set individually for function Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 4 to the following function pins AM1 AM0 Function Setting after reset is released 0 0 1 1 0 1 0 1 Don t use this setting Address bus A0 to A7 Address bus A0 to A7 Don t use this setting Figure 3 7 3 Port4 P4FC Register P4 Register S 0 1 Selector A0 to A7 Read data P40 ...

Page 96: ...F P44F P43F P42F P41F P40F Read Write W System Reset State 1 1 1 1 1 1 1 1 P4FC 0013H Function 0 Port 1 Address bus A0 to A7 Port 4 Drive register 7 6 5 4 3 2 1 0 bit Symbol P47D P46D P45D P44D P43D P42D P41D P40D Read Write R W System Reset State 1 1 1 1 1 1 1 1 P4DR 0084H Function Input Output buffer drive register for standby mode Note A read modify write operation cannot be performed for P4FC ...

Page 97: ...Each bit can be set individually for function Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 5 to the following function pins AM1 AM0 Function Setting after reset is released 0 0 1 1 0 1 0 1 Don t use this setting Address bus A8 A15 Address bus A8 A15 Don t use this setting Figure 3 7 5 Port5 P5FC Register P5 Register S 0 1 Selector A8 to A15 Read data P50 to ...

Page 98: ...F P54F P53F P52F P51F P50F Read Write W System Reset State 1 1 1 1 1 1 1 1 P5FC 0017H Function 0 Port 1 Address bus A8 to A15 Port 5 Drive register 7 6 5 4 3 2 1 0 bit Symbol P57D P56D P55D P54D P53D P52D P51D P50D Read Write R W System Reset State 1 1 1 1 1 1 1 1 P5DR 0085H Function Input Output buffer drive register for standby mode Note A read modify write operation cannot be performed for P5FC...

Page 99: ...ose I O port port6 can also function as an address bus A16 to A23 Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 6 to the following function pins AM1 AM0 Function Setting after reset is released 0 0 1 1 0 1 0 1 Don t use this setting Address bus A16 A23 Address bus A16 A23 Don t use this setting Figure 3 7 7 Port6 P6CR Register P6FC Register P6 Register S 0 1 ...

Page 100: ...01AH Function 0 Input 1 Output Port 6 Function register 7 6 5 4 3 2 1 0 bit Symbol P67F P66F P65F P64F P63F P62F P61F P60F Read Write W System Reset State 1 1 1 1 1 1 1 1 P6FC 001BH Function 0 Port 1 Address bus A16 to A23 Port 6 Drive buffer register 7 6 5 4 3 2 1 0 bit Symbol P67D P66D P65D P64D P63D P62D P61D P60D Read Write R W System Reset State 1 1 1 1 1 1 1 1 Hot Reset State P6DR 0086H Func...

Page 101: ...ializes P70 pin to output port mode and P71 to P76 pins to input port mode Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 7 to the following function pins Initial setting of P70 pin AM1 AM0 Function Setting after reset is released 0 0 1 1 0 1 0 1 Don t use this setting RD pin RD pin Don t use this setting Figure 3 7 9 Port7 P7 register S 0 1 Selector Port read...

Page 102: ...ister S 1 0 Selector P7CR register P7FC register S 0 1 Selector P73 EA24 P74 EA25 EA24 EA25 Selector P7 register Port read data P7CR register P7FC register S 1 0 S 0 1 NDR B P75 R W B NDR R W Selector P76 WAIT P7 register P7CR register P7FC register WAIT Port read data ...

Page 103: ... 7 Drive register 7 6 5 4 3 2 1 0 bit Symbol P76D P75D P74D P73D P72D P71D P70D Read Write R W System Reset State 1 1 1 1 1 1 1 P7DR 0087H Function Input Output buffer drive register for standby mode Note1 A read modify write operation cannot be performed for P7CR P7FC Note2 When NDRE and NDWE are used set registers in the following order to avoid outputting a negative glitch Order Registser bit2 ...

Page 104: ... register P8FC Writing 1 in the corresponding bit of P8FC and P8FC2 enables the respective functions Resetting P8FC to 0 and P8FC2 to 0 sets all bits to output ports Figure 3 7 12 Port 8 P80 0 CS P81 1 CS SDCS P82 2 CS CSZA SDCS P83 3 CS CSXA P86 CSZD CE 0 ND P87 CSXB CE 1 ND Function control Output latch P8 read Reset 0 CS 1 CS 2 CS 3 CS CSZD CSXB Selector P8FC write P8 write S Function control2 ...

Page 105: ... bit Symbol P87D P86D P83D P82D P81D P80D Read Write R W R W System Reset State 1 1 1 1 1 1 P8DR 0088H Function Input Output buffer drive register for standby mode Note1 A read modify write operation cannot be performed for P8FC and P8FC2 Note2 Do not write 1 to P8 P82 register before setting P82 pin to 2 CS or CSZA because on reset P82 pin outputs 0 as CE for program memory Note3 When CE 0 ND and...

Page 106: ...rpose I O port They are also function as either SIO0 or SIO1 SIO0 and SIO1 functions are also used as PP3 to PP5 pins When selecting SIO0 function using Port 9 or Port P set P9FC2 P93F2 P94F2 P95F2 And when selection SIO1 function using Port 9 or Port P set PPFC2 PP4F2 PP5F2 PP6F2 SIO mode SIO0 module UART IrDA mode SIO0 module P90 TXD0 TXD1 Data output TXD0 Data output P91 RXD0 RXD1 Data input RX...

Page 107: ... P96 AVCC Switch for TSI typ 10Ω Pull down resistor typ 50kΩ B TSICR0 TWIEN TSI7 Internal data bus Internal data bus Selector A B S Selector A B S P91 RXD0 RXD1 P92 SCLK0 0 CTS SCLK1 1 CTS P9 read Direction control on bit basis P9CRwrite Function control on bit basis S Output latch P9 write Reset P9FCwrite RXD0 input SCLK0 input 0 CTS input SCLK0 output SCLK1 output Selector S A B P9FC2 P95F2 Sele...

Page 108: ...ollowing table Port 9 function register 7 6 5 4 3 2 1 0 bit Symbol P96F P92F P90F Read Write W W W System Reset State 0 0 0 P9FC 0027H Function 0 Input port 1 INT4 Refer to following table Refer to following table Port 9 Function registers 2 7 6 5 4 3 2 1 0 bit Symbol P95F2 P94F2 P93F2 P90F2 Read Write W W W W W W System Reset State 0 0 0 0 0 0 P9FC2 0025H Function Always write 0 P92 SCLK selectio...

Page 109: ...NT4 input set P9DR P96D to 0 prohibit input and when driving P96 pin to 0 execute HALT instruction This setting generates INT4 inside If don t using external interrupt in HALT condition set like an interrupt don t generated e g change port setting Figure 3 7 17 Register for Port 9 P90C P90F 0 1 0 Input port Output port 1 Don t setting TXD0 TXD1 Output P90 setting P91C 0 1 Input port RXD0 RXD1 Inpu...

Page 110: ...abled by writing a 1 to the corresponding bit of the Port A Function Register PAFC Resetting resets all bits of the register PAFC to 0 and sets all pins to be input port Figure 3 7 18 Port A When PAFC 1 if the input of any of KI0 KI7 pins falls down an INTKEY interrupt is generated An INTKEY interrupt can be used to release all HALT modes Internal data bus PA0 to PA7 KI0 to KI7 INTKEY Rising edge ...

Page 111: ...5F PA4F PA3F PA2F PA1F PA0F Read Write W System Reset State 0 0 0 0 0 0 0 0 PAFC 002BH Function 0 KEY IN disable 1 KEY IN enable Port A Drive register 7 6 5 4 3 2 1 0 bit Symbol PA7D PA6D PA5D PA4D PA3D PA2D PA1D PA0D Read Write R W System Reset State 1 1 1 1 1 1 1 1 PADR 008AH Function Input Output buffer drive register for standby mode Note A read modify write operation cannot be performed for P...

Page 112: ...nal interruption INT0 to INT3 Extension address function EA26 EA27 EA28 output pin for SPI controller SPDI SPDO and SPCLK and output pin for Key KO8 These settings are mode using the function register PCFC The edge select for external interruption is determined by the IIMC register in the interruption controller 1 PC0 INT0 PC2 INT2 Figure 3 7 20 Port C0 C2 PC0 INT0 PC2 INT2 Internal data bus Direc...

Page 113: ... 7 21 Port C1 C3 PC1 INT1 TA0IN PC3 INT3 TA2IN Internal data bus Direction control Reset PCCR write PCwrite PC read Function control PCFCwrite S Output latch S B Selector A Level edge selection and Rising Falling selection IIMC I1LE I1EDGE I3LE I3EDGE INT1 INT3 TA0IN TA2IN ...

Page 114: ...write Function control on bit basis PCFC write S Output latch PC write Reset Selector S Internal data bus A B EA26 Selector B S A PCFC2 PC4F2 from PR0 SPDI SPDI input PC5 EA27 SPDO PC6 EA28 SPCLK Selector B A S PC read Direction control on bit basis PCCR write Function control on bit basis PCFC write S Output latch PC write Reset Selector S SPDO SPCLK Internal data bus A B C D EA27 EA28 ...

Page 115: ...0 2009 06 12 92CF30 113 5 PC7 KO8 Figure 3 7 24 Port C7 Reset Selector A B S PC7 KO8 PC read Direction control PCCR write Function control PCFC write S Output latch PC write Open drain enable Internal data bus ...

Page 116: ...ol PC7C PC6C PC5C PC4C PC3C PC2C PC1C PC0C Read Write W System Reset State 0 0 0 0 0 0 0 0 PCCR 0032H Function 0 Input 1 Output Port C function register 7 6 5 4 3 2 1 0 bit Symbol PC7F PC6F PC5F PC4F PC3F PC2F PC1F PC0F Read Write W System Reset State 0 0 0 0 0 0 0 0 PCFC 0033H Function Refer to following table Port C function register 2 7 6 5 4 3 2 1 0 bit Symbol PC4F2 Read Write W System Reset S...

Page 117: ... external interrupt in HALT condition set like an interrupt don t generated e g change port setting Figure 3 7 25 Register for Port C PC0C PC0F 0 1 0 Input port Output port 1 INT0 Don t setting PC0 setting PC1C PC1F 0 1 0 Input port Output port 1 INT1 TA0IN input PC1 setting PC2C PC2F 0 1 0 Input port Output port 1 INT2 Don t setting PC2 setting PC3C PC3F 0 1 0 Input port Output port 1 INT3 TA2IN ...

Page 118: ...utput for I2S0 A pin can be enabled for I O by writing a 1 to the corresponding bit of the Port F Function Register PFFC Port F7 is a 1 bit general purpose output port In addition to functioning as general purpose output port PF7 can also function as the SDCLK output Resetting sets PF7 to be an SDCLK output port 1 Port F0 I2S0CKO Port F1 I2S0DO Port F2 I2S0WS Ports F0 to F2 are general purpose I O...

Page 119: ...CLK output Figure 3 7 27 Port F7 Internal data bus Selector A B S Selector A B S PF0 I2S0CKO PF1 I2S0DO PF2 I2S0WS I2S0CKO output I2S0DO output I2S0WS output PF read Direction control on bit basis PFCR write Function control on bit basis S Output latch PF write Reset PFFC write SDCLK Selector A B S PF7 SDCLK PF read Function control on bit basis PFFC write S Output latch PF write Reset Internal da...

Page 120: ...PF0F Read Write W W System Reset State 1 0 0 0 PFFC 003FH Function 0 Port 1 SDCLK Refer to following table Port F drive register 7 6 5 4 3 2 1 0 bit Symbol PF7D PF2D PF1D PF0D Read Write R W R W System Reset State 1 1 1 1 PFDR 008FH Function Input Output buffer drive register for standby mode Note A read modify write operation cannot be performed for the registers PFCR PFFC Figure 3 7 28 Register ...

Page 121: ... for a Touch screen interface PG register is prohibited to access by byte All the instruction Arithmetic Logical Bit operation and rotate shift instruction accesses by byte are prohibited Word access is always needed Figure 3 7 29 Port G AD read Conversion Result Register AD Converter Channel Selector Port G read PG0 AN0 PG1 AN1 PG2 AN2 MX PG3 AN3 MY ADTRG PG4 AN4 PG5 AN5 ADTRG for PG3 only TSICR0...

Page 122: ...D converter mode register ADMOD1 Port G Function register 7 6 5 4 3 2 1 0 Bit Symbol PG3F Read Write W System Reset State 0 Hot Reset State PGFC 0043H Function 0 Input port or AN3 1 ADTRG Port G driver register 7 6 5 4 3 2 1 0 Bit Symbol PG3D PG2D Read Write R W System Reset State 1 1 Hot Reset State PGDR 0090H Function Input Output buffer drive register for standby mode Note A read modify write o...

Page 123: ... SRLLB SRLUB SRULB and SRUUB and NAND Flash NDALE and NDCLE The above settings are made using the function register PJFC However either SDRAM or SRAM output signal for PJ0 to PJ2 are selected automatically according to the setting of the memory controller Figure 3 7 31 Port J0 to J4 and J7 S Function control on bit basis Output latch PJ read Reset PJ0 SDRAS SRLLB PJ1 SDCAS SRLUB PJ2 SDWE SRWR PJ3 ...

Page 124: ...ure 3 7 32 Port J5 J6 Internal data bus A B S Selector A B S PJ5 NDALE SRULB PJ6 NDCLE SRUUB NDALE NDCLE output PJ read Direction control PJCR write Function control S Output latch PJ write Reset PJFC write Selector C SRULB SRUUB output ...

Page 125: ...set State 0 0 0 0 0 0 0 0 PJFC 004FH Function 0 Port 1 SDCKE Refer to following table 0 Port 1 SDLUDQM 0 Port 1 SDLLDQM 0 Port 1 SDWE SRWR 0 Port 1 SDCAS SRLUB 0 Port 1 SDRAS SRLLB Port J drive register 7 6 5 4 3 2 1 0 bit Symbol PJ7D PJ6D PJ5D PJ4D PJ3D PJ2D PJ1D PJ0D Read Write R W System Reset State 1 1 1 1 1 1 1 1 PJDR 0093H Function Input Output buffer drive register for standby mode Note A r...

Page 126: ... 3 7 13 Port K PK0 to PK7 PK0 to PK7 are 8 bit output ports Resetting sets the output latch PK to 0 and PK0 to PK7 pins output 0 Figure 3 7 34 Port K0 to K7 Output latch PK read PK0 PK7 Output buffer PK write Internal data bus Reset ...

Page 127: ...K0 Read Write R W PK 0050H System Reset State 0 0 0 0 0 0 0 0 Port K drive register 7 6 5 4 3 2 1 0 bit Symbol PK7D PK6D PK5D PK4D PK3D PK2D PK1D PK0D Read Write R W System Reset State 1 1 1 1 1 1 1 1 PKDR 0094H Function Input Output buffer drive register for standby mode Figure 3 7 35 Register for Port K ...

Page 128: ...d the function register PLFC Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 1 to the following function pins AM1 AM0 Function Setting after reset is released 0 0 1 1 0 1 0 1 Don t use this setting Input port PL0 PL7 Data bus D16 D23 Don t use this setting Figure 3 7 36 Port L0 to L7 PLCR register PLFC2 register PL register S External write enable D16 to D23 Po...

Page 129: ... W System Reset State 0 0 0 0 0 0 0 0 PLFC 0057H Function 0 Port 1 Don t setting Port L function register 2 7 6 5 4 3 2 1 0 bit Symbol PL0F2 Read Write W System Reset State 0 1 PLFC2 0055H Function 0 Port 1 Data bus D16 D23 Port L drive register 7 6 5 4 3 2 1 0 bit Symbol PL7D PL6D PL5D PL4D PL3D PL2D PL1D PL0D Read Write R W System Reset State 1 1 1 1 1 1 1 1 PLDR 0095H Function Input Output buff...

Page 130: ...T output pins for the RTC alarm ALARM and as the output pin for the melody alarm generator MLDALM MLDALM The above settings are made using the function register PMFC PM1 has two output function which MLDALM and TA1OUT and PM2 has two output functions ALARM and MLDALM These are selected using PM PM1 PM PM2 Figure 3 7 38 Port M1 MLDALM Reset S Output latch PM write PM read Function control PMFC writ...

Page 131: ... M7 Reset S Output latch PM write PM read Function control on bit basis PMFC write S A Selector PM7 Internal data bus MLDALM Reset S Output latch PM write PM read Function control on bit basis PMFC write S A Selector B ALARM PM2 ALARM MLDALM A S Selector B Internal data bus ...

Page 132: ...H Function 0 Port 1 Don t setting 0 Port 1 ALARM at PM2 1 MLDALM at PM2 0 0 Port 1 MLDALM at PM1 1 TA1OUT at PM1 0 Port M drive register 7 6 5 4 3 2 1 0 bit Symbol PM7D PM2D PM1D Read Write R W R W System Reset State 1 1 1 PMDR 0096H Function Input Output buffer drive register for standby mode Input Output buffer drive register for standby mode Note A read modify write operation cannot be performe...

Page 133: ...nput port In addition to functioning as a general purpose I O port Port N can also function as key board interface pin KO0 to KO7 which can be set to open drain output buffer Figure 3 7 42 Port N Selector A B S PN0 KO0 to PN7 KO7 PC read Direction control on bit basis PNCR write Function control on bit basis PNFC write S Output latch PN write Reset Open drain enable Internal data bus ...

Page 134: ...5EH Function 0 Input 1 Output Port N function register 7 6 5 4 3 2 1 0 bit Symbol PN7F PN6F PN5F PN4F PN3F PN2F PN1F PN0F Read Write W System Reset State 0 0 0 0 0 0 0 0 PNFC 005FH Function 0 CMOS output 1 Open drain output Port N drive register 7 6 5 4 3 2 1 0 bit Symbol PN7D PN6D PN5D PN4D PN3D PN2D PN1D PN0D Read Write R W System Reset State 1 1 1 1 1 1 1 1 PNDR 0097H Function Input Output buff...

Page 135: ...d PP7 can also function as an output pin for timer TB0OUT0 Setting in the corresponding bits of PPCR and PPFC enables the respective functions The edge select for external interruption is determined by the IIMC register in the interruption controller In port setting if 16 bit timer input is selected and capture control is executed INT6 and INT7 don t depend on IIMC1 register setting INT6 and INT7 ...

Page 136: ...Internal data bus Direction control on bit basis Reset PPCR write PP write PP read Function control on bit basis PPFC write R Output latch S B Selector A Rising Falling selection IIMC0 I6EDGE INT6 from TMRB0 INT6 A Selector B S PP5F2 PP2F2 P91RXD1 from P91 to P91 PP4RXD0 RXD1 input PP2F2 ...

Page 137: ...trol on bit basis Reset PPCR write PP write PP read Function control on bit basis PPFC write R Output latch S B Selector A Rising Falling selection IIMC I7EDGE IINT7 from TMRB1 INT7 A Selector B S PP6F2 PP3F2 P92SCLKI1 from P92 to P92 PP5SCLKI0 SCLK1 input 1 CTS input PP3F2 Selector B A S Selector B A S SCLK1 SCLK0 PP6F2 PP3F2 PP3F2 ...

Page 138: ...TMP92CF30 2009 06 12 92CF30 136 Figure 3 7 47 Port P6 Selector A B S PP6 TB0OUT0 TB0OUT0 output Function control on bit basis R Output latch PP write Reset PPFC write Internal data bus ...

Page 139: ...l PP5C PP4C PP3C Read Write W System Reset State 0 0 0 PPCR 0062H Function 0 Input 1 Output Port P function register 7 6 5 4 3 2 1 0 bit Symbol PP6F PP5F PP4F PP3F Read Write W System Reset State 0 0 0 0 PPFC 0063H Function 0 Port 1 TB0OUT0 Refer to following table Port P drive register 7 6 5 4 3 2 1 0 bit Symbol PP6D PP5D PP4D PP3D Read Write R W System Reset State 1 1 1 1 PPDR 0098H Function Inp...

Page 140: ...3 is set to TXD PP4 is set to RXD PP5 is set to SCLK input or CTS input when PP5C 0 PP5 is set to SCLK output when PP5C 1 Note2 A read modify write operation cannot be performed for the registers PPCR PPFC Note3 When setting PP5 PP4 PP3 pins to INT7 INT6 INT5 input set PPDR PP5D 3D to 0000 prohibit input and when driving PP5 PP4 PP3 pins to 0 execute HALT instruction This setting generates INT7 IN...

Page 141: ... In addition to functioning as general purpose I O port PR0 to PR3 can also function as the SPI controller pin SPCLK SPCS SPDO and SPDI Setting in the corresponding bits of PFCR and PFFC enables the respective functions Figure 3 7 49 Port R0 Selector A B S PR0 SPDI PR read Direction control on bit basis PRCR write Function control on bit basis PRFC write R Output latch PR write Reset to Port C SPD...

Page 142: ...ure 3 7 50 Port R1 to R3 Selector A B S PR1 SPDO PR2 SPCS PR3 SPCLK PR read Direction control on bit basis PRCR write Function control on bit basis PRFC write R Output latch PR write Reset Selector A B S SPDO SPCS SPCLK Internal data bus ...

Page 143: ...67H Function 0 Port 1 SPCLK 0 Port 1 SPCS 0 Port 1 SPDO 0 Port 1 SPDI Port R drive register 7 6 5 4 3 2 1 0 bit Symbol PR3D PR2D PR1D PR0D Read Write R W System Reset State 1 1 1 1 PRDR 0099H Function Input Output buffer drive register for standby mode Note A read modify write operation cannot be performed for the registers PRCR PRFC Figure 3 7 51 Register for Port R PR0C PR0F 0 1 0 Input port Out...

Page 144: ...bove setting is used the control register PTCR and function register PTFC Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 1 to the following function pins AM1 AM0 Function Setting after reset is released 0 0 1 1 0 1 0 1 Don t use this setting Input port PT0 PT7 Data bus D24 D31 Don t use this setting Figure 3 7 52 Port T0 to T7 PTCR register PTFC2 register PT r...

Page 145: ...PT0F Read Write W System Reset State 0 0 0 0 0 0 0 0 PTFC 00A3H Function 0 Port 1 Don t setting Port T function register 2 7 6 5 4 3 2 1 0 bit Symbol PT0F2 Read Write After system reset 0 1 After Hot reset PTFC2 00A1H Function 0 Port 1 Data bus D24 to D31 Port T drive register 7 6 5 4 3 2 1 0 bit Symbol PT7D PT6D PT5D PT4D PT3D PT2D PT1D PT0D Read Write R W System Reset State 1 1 1 1 1 1 1 1 PTDR ...

Page 146: ...g as general purpose I O port PV can also function as a input or output pin for SBI SDA SCL Setting in the corresponding bits of PVCR and PVFC enables the respective functions Figure 3 7 54 Port V6 V7 Selector B D S Selector B A S PV6 SDA PV7 SCL PV read Direction control on bit basis PVCR write Function control on bit basis PVFC write R Output latch PV write Reset SDA SCL output Internal data bus...

Page 147: ...unction Refer to following table Port V function register 2 7 6 5 4 3 2 1 0 bit Symbol PV7F2 PV6F2 Read Write W System Reset State 0 0 PVFC2 00A9H Function 0 CMOS 1 Open drain 0 CMOS 1 Open drain Port V drive register 7 6 5 4 3 2 1 0 bit Symbol PV7D PV6D Read Write R W System Reset State 1 1 PVDR 009DH Function Input Output buffer drive register for standby mode Note A read modify write operation ...

Page 148: ...X2 oscillation clock X1D4 Setting in the corresponding bits of PXCR and PXFC enables the respective functions Port X4 is 1 bit general purpose output port Resetting sets output latch to 0 In addition to functioning as general purpose output port PX4 can also function as a system clock output pin CLKOUT Setting in the corresponding bits of PX and PXFC enables the respective functions Figure 3 7 56 ...

Page 149: ...X read Direction control on bit basis PXCR write Function control on bit basis PXFC write R Output latch PX write Reset Internal data bus X1USB input Selector X1D4 output Function control 2 on bit basis PXFC2 write Selector S X1pin 1 8 X1 pin 1 4 X1 pin 1 2 X1 pin 1 1 Selector B S S A B ...

Page 150: ...PX5C Read Write W System Reset State 0 PXCR 00B2H Function 0 Input 1 Output Port X function register 7 6 5 4 3 2 1 0 bit Symbol PX5F PX4F Read Write W System Reset State 0 0 PXFC 00B3H Function Refer to following table 0 Port 1 CLKOUT at PX4 0 Port X function register 2 7 6 5 4 3 2 1 0 bit Symbol PX5F2 PX4F2 Read Write R W System Reset State 0 0 PXFC2 00B1H Function X1D4 output clock selection 00 ...

Page 151: ...t be performed for the registers PXCR PXFC and PXFC2 Note 2 When PX4 is used as CLKOUT output pin PX PX4 must be set to 0 Refer to following PX4 setting table Note 3 When PX5 is used as X1D4 pin PX PX5 must be set to 1 Refer to following PX5 setting table Figure 3 7 58 Register for Port X PX4 PX4F 0 1 0 Output port 1 CLKOUT output Don t setting PX4 setting PX5C PX5F 0 1 0 Input port Output port 1 ...

Page 152: ...n an external area to avoid data conflicts with CS spaces 2 Memory specification The MEMC can specify the type of memory SRAM ROM and SDRAM to associate with the selected address spaces 3 Data bus width specification The data bus width is selectable from 8 16 and 32 bits for the respective chip select spaces Howerver SDRAM and NANDF cannot use 32 bit data bus 4 Wait control The number of wait stat...

Page 153: ... memory controller such as the memory type specification and the number of wait states to be inserted into a read or write cycle Memory Start Address register MSARn n 0 to 3 Specifies a start address fora selected address space Memory Address Mask register MAMR n 0 to 3 Specifies a block size for a selected address space Page ROM Control register PMEMCR Selects a method of accessing Page ROM Timin...

Page 154: ...et State 1 1 1 1 1 1 1 1 Bit Symbol M1S23 M1S22 M1S21 M1S20 M1S19 M1S18 M1S17 M1S16 Read Write R W MSAR1 0147H Reset State 1 1 1 1 1 1 1 1 Bit Symbol B2WW3 B2WW2 B2WW1 B2WW0 B2WR3 B2WR2 B2WR1 B2WR0 Read Write R W B2CSL 0148H Reset State 0 0 1 0 0 0 1 0 Bit Symbol B2E B2M B2REC B2OM1 B2OM0 B2BUS1 B2BUS0 Read Write R W R W B2CSH 0149H Reset State 1 0 0 0 0 0 1 Bit Symbol M2V22 M2V21 M2V20 M2V19 M2V1...

Page 155: ...SEL0 TAC1 TAC0 Read Write R W R W CSTMGCR 0168H Reset State 0 0 0 0 Bit Symbol TCWSEL1 TCWSEL0 TCWS1 TCWS0 TCWH1 TCWH0 Read Write R W R W R W WRTMGCR 0169H Reset State 0 0 0 0 0 0 Bit Symbol B1TCRS1 B1TCRS0 B1TCRH1 B1TCRH0 B0TCRS1 B0TCRS0 B0TCRH1 B0TCRH0 Read Write R W R W R W R W RDTMGCR0 016AH Reset State 0 0 0 0 0 0 0 0 Bit Symbol B3TCRS1 B3TCRS0 B3TCRH1 B3TCRH0 B2TCRS1 B2TCRS0 B2TCRH1 B2TCRH0 ...

Page 156: ...t any other timing Upon reset only the control registers B2CSH and B2CSL for the CS2 space automatically becomes effective The B2CSH B2E bit is set to 1 upon reset Then the AM1 and AM0 values that specify the data bus width are loaded into the data bus width specification bits of the control register for the CS2 space At the same time the address range ebtween 000000H and FFFFFFH is defined as the...

Page 157: ... A15 to A0 are assumed to be 0 Accordingly the start address can only be a multiple of 64 Kbytes ranging from 000000H to FF0000H Figure 3 8 2 shows the relationship between the start addresses and the Memory Start Address register values Memory Start Address Registers for CS0 to CS3 spaces 7 6 5 4 3 2 1 0 Bit Symbol S23 S22 S21 S20 S19 S18 S17 S16 MSAR0 0143H MSAR1 0147H Read Write R W Reset State...

Page 158: ... defined as the CS2 space The B2M bit is cleared to 0after reset By setting the B2CSH B2M bit to 1 the start address and the block size can be arbitrarily specified as in the other spaces Memory Address Mask Register for CS0 space 7 6 5 4 3 2 1 0 Bit Symbol V20 V19 V18 V17 V16 V15 V14 9 V8 Read Write R W Reset State 1 1 1 1 1 1 1 1 MAMR0 0142H Function CS0 block size 0 The address compare logic us...

Page 159: ... Kbytes Memory address mask register setting MSAR0 MSMR0 Setting of 07H specifies a 64 Kbyte area H 0 d Programming block sizes Table 3 8 3 shows the relationship between CS spaces and their block sizes The Δ symbol indicates the size that might not be programmable depending on the combination of the values of the Memory Start Address and Memory Address Mask registers When specifying a block size ...

Page 160: ...dress Mask registers e Priorities of the address spaces When the specified address space overlaps with the on chip memory area the priority order of the address spaces are as follows f Specifying the number of wait states and the bus width for the address locations outside the CS0 to CS3 spaces The BEXCSL and BEXCSH registers specify the data bus width and number of wait states when an address out...

Page 161: ...de Default 0 1 16 bit bus mode 1 0 32 bit bus mode 1 1 Don t use this setting Note The data bus width for SDRAM should be defined as 16 bits by setting BnCSH BnBUS1 BnBUS0 to 01 As described above the TMP92CF30 supports dinamic bus sizing which allows the controller to transfer operands to or from the selected address spaces while automatically determining the data bus width On which part of the d...

Page 162: ...3 4n 2 xxxxx xxxxx xxxxx b23 to b16 8 4 4n 3 xxxxx xxxxx xxxxx b31 to b24 1 4n 0 xxxxx xxxxx b15 to b8 b7 to b0 16 2 4n 2 xxxxx xxxxx b31 to b24 b23 to b16 4n 0 32 4n 0 b31 to b24 b23 to b16 b15 to b8 b7 to b0 1 4n 0 xxxxx xxxxx xxxxx b7 to b0 2 4n 1 xxxxx xxxxx xxxxx b15 to b8 3 4n 2 xxxxx xxxxx xxxxx b23 to b16 8 4 4n 3 xxxxx xxxxx xxxxx b31 to b24 1 4n 1 xxxxx xxxxx b7 to b0 xxxxx 2 4n 2 xxxxx ...

Page 163: ...tes 8 wait states fixed wait state mode 1 1 0 0 11 states 9 wait states fixed wait state mode 1 1 0 1 12 states 10 wait states fixed wait state mode 1 1 1 0 14 states 12 wait states fixed wait state mode 1 1 1 1 18 states 16 wait states fixed wait state mode 0 1 0 0 22 states 20 wait states fixed wait state mode 0 0 1 1 6 states WAIT pin input mode Other than the above Reserved Note 1 For SDRAM th...

Page 164: ...roblem a single dummy cycle can be inserted immediately after an access cycle for the CSm space by setting the BmCSH BmREC bit to 1 This single dummy cycle is inserted when another CS space is accessed in the next bus cycle BnCSH BnREC 0 No dummy cycle is inserted Default 1 Dummy cycle is inserted When no dummy cycle is inserted 0 wait state When a single dummy cycle is inserted 0 wait state SDCLK...

Page 165: ...em operate with basic bus timing Refer to 7 This function can not be used while the BnCSH BnREC bit is enabled The control signals of SDRAM can be adjusted by setting up the SDRAM controller CSTMGCR TxxSEL1 TxxSEL0 WRTMGCR TxxSEL1 TxxSEL0 00 Change the bus timing for CS0 space 01 Change the bus timing for CS1 space 10 Change the bus timing for CS2 space 11 Change the bus timing for CS3 space CSTMG...

Page 166: ...D SRxxB Note1 Wait states TWs are inserted as specified by the BnCSL register No TW is inserted if the number of wait state is specified as zero Note2 Above diagram shows case of 32 bit bus access A23 to A0 CSn R W T1 T2 SDCLK 80MHz RD SRxxB Input D31 to D0 Read cycle T3 Tn TAC TCRS TCRH Tn 1 WRxx SRWR SRxxB D31 to D0 TCWS TCWH TAC Output Tn 2 Write cycle Output TCWS TW ...

Page 167: ...se of 32 bit bus access b External bus read write cycle 1 wait state Note Above diagram shows case of 32 bit bus access CSn WRxx RD SRxxB A23 to A0 Input Output Read Write SDCLK 80 MHz D31to D0 D31 to D0 T1 T2 SRWR SRxxB CSn WRxx RD SRxxB A23 to A0 Output SDCLK 80 MHz D31 to D0 D31 to D0 T1 TW Input Read Write T2 SRWR SRxxB ...

Page 168: ...f 32 bit bus access d External bus read write cycle 4 wait states WAIT pin input mode Note Above diagram shows case of 32 bit bus access Read T1 T6 Input Output Write T2 T3 T4 T5 TAC TAC TCRS TCRH TCWS TCWH TCWS TCWH D31 to D0 A23 to A0 D31 to D0 WRxx SDCLK 80 MHz RD SRxxB SRWR SRxxB CSn Write Sampling Read T1 T6 Input Output T2 T3 T4 T5 D31 to D0 A23 to A0 D31 to D0 WRxx SDCLK 80 MHz RD SRxxB SRW...

Page 169: ... 1 fSYS External bus write cycle 4 wait states WAIT pin input mode TAC 1 1 fSYS TCWS H 1 5 1 fSYS Note Above diagram shows case of 32 bit bus access Sampling Read T1 T6 Input Output Write T2 T3 T4 T5 TW Sampling D31 to D0 A23 to A0 D31 to D0 WRxx SDCLK 80 MHz RD SRxxB SRWR SRxxB CSn WAIT Sampling Read T1 T9 Input Output Write T2 T3 T4 T7 TW Sampling T8 T10 D31 to D0 A23 to A0 D31 to D0 WRxx SDCLK ...

Page 170: ... how to connect external 16 bit SRAM and 16 bit NOR flash to the TMP92CF30 Figure 3 8 4 Example of External 16 Bit SRAM and NOR Flash Connection 16 bit SRAM RD SRLLB SRLUB SRWR 0 CS D 15 0 A0 A1 A2 A3 2 CS OE LDS UDS R W CE I O 16 1 A0 A1 A2 16 bit NOR flash OE WE CE DQ 15 0 A0 A1 A2 Not connect ...

Page 171: ...PWR0 OPWR1 OPWR0 Number of Cycles in Page Mode 0 0 1 cycle n 1 1 1 mode n 2 0 1 2 cycles n 2 2 2 mode n 3 1 0 3 cycles n 3 3 3 mode n 4 1 1 4 cycles n 4 4 4 mode n 5 Note Specify the number of wait states n using the control register BnCSL for each address space The page size the number of bytes of ROM as seen from the CPU is determined by PMEMCR PR1 PR0 When the specified page boundary is reached...

Page 172: ...mmands the toggle bit may not be read correctly If the rising edge of the read signal in the cycle immediately preceding the NOR flash access cycle does not occur in time a read cycle may be extended unintentilnally as indicated as b in Figure 3 8 7 Figure 3 8 7 NOR Flash Toggle Bit Read Cycle When the toggle bit is inverted due to this unexpected read cycle extension the CPU cannot read the toggl...

Page 173: ...ea 001FF0H to 001FFFH is predefined asNAND Flash area as shown below regardless of which CS space is selected Therefore the setting of the CS3 space does not affect the NAND flash area NAND Flash area specification 1 Bus width Specified by NDFMCR1 BUSW in the NAND Flash controller 2 Wait control Specified by NDFMCR SPLW1 SPLW0 and NDFMCR SPHW1 SPHW0 in the NAND Flash controller 7 6 5 4 3 2 1 0 Bit...

Page 174: ... a data conflict To avoid this it is recommended that the 32 Kbyte memory area from 000000H to 007FFFH be assigned to the CS0 space The CS0 pin is not required Since the CS0 setting has higher priority over the settings of the CS2 and CS1 spaces only NAND flash will be accessed without causing data conflicts Note In this case the 32 Kbyte memory area from 000000H to 007FFFH within the SDCS space c...

Page 175: ...ly a series of program routines should be stored entirely within one bank The program execution cannot be branched between different banks of the same LOCAL area using the JP instruction For more details refer to the following programming examples The TMP92CF30 has the following external pins for connecting external memory Address bus EA28 EA27 EA26 EA25 EA24 and A23 to A0 Chip Select 0 CS to 3 CS...

Page 176: ... area which cannot be configured as LOCAL area 400000H 800000H C00000H FFFF00H FFFFFFH Address memory map LOCAL Z 4 MB COMMON Z 4 MB Bank 0 1 2 3 127 128 255 384 511 600000H LOCAL Y 2 MB COMMON Y 2 MB Bank 0 1 2 3 15 Bank 0 1 2 3 15 200000H LOCAL X 2 MB COMMON X 2 MB On chip I O RAM CSZA pin Note 1 512 MB 4 MB 128 Cannot access CSZD pin SDCS 64 MB when connecting SDRAM 2MB 32 Note 2 or 1 CS pin 12...

Page 177: ...nk 63 Bank 0 Bank 127 Bank 384 Bank 511 Bank 255 Bank 511 CSXA CSXB Bank256 383 Bank256 In TMP92CF30 there are not it on the external that chip select pins for from 256 to 383 Banks of local Z area Therefore its area cannot be accessed Don t use 256 to 383 Banks Note In case of connecting SDRAM to the Y area the maximum expanded memory size is 64MB 2MB 32 Figure 3 9 2 Recommended Memory Map for th...

Page 178: ...the LOCAL area changing Program bank number LOCALPX Y or Z is disabled Program bank setting of each LOCAL area must change in COMMON area But bank setting of data Read and data Write can change also in LOCAL area Note3 After setting values specifying the data bank number into bank registers for the read write and DMA data LOCALRn LOCALWn or LOCALLn LOCALESn LOCALEDn LOCALOSn LOCALODn the symbol n ...

Page 179: ...111 CSXA 100000000 to 111111111 CSXB LOCAL Y Register for Program 7 6 5 4 3 2 1 0 Bit Symbol Y5 Y4 Y3 Y2 Y1 Y0 Read Write R W Reset State 0 0 0 0 0 0 Function Specify the bank number for the LOCAL Y area Since bank 3 is overlapping with the COMMON area this filed must not be specified as 3 LOCALPY 0882H 15 14 13 12 11 10 9 8 Bit Symbol LYE Read Write R W 0883H Reset State 0 Function Bank for LOCAL...

Page 180: ...r for Read Data 7 6 5 4 3 2 1 0 Bit Symbol X7 X6 X5 X4 X3 X2 X1 X0 Read Write R W Reset State 0 0 0 0 0 0 0 0 Function Specify the bank number for the LOCAL X area Since bank 0 is overlapping with the COMMON area this filed must not be specified as 0 LOCALRX 0890H 15 14 13 12 11 10 9 8 Bit Symbol LXE X8 Read Write R W R W 0891H Reset State 0 0 Function Bank for LOCAL X 0 Disable 1 Enable Specify t...

Page 181: ...MMON area this filed must not be specified as 3 LOCALRZ 0894H 15 14 13 12 11 10 9 8 Bit Symbol LZE Z8 Read Write R W R W 0895H Reset State 0 0 Specify the bank number for the LOCAL Z area Settings of the X8 through X0 bits and their corresponding chip select signals Function Bank for LOCAL Z 0 Disable 1 Enable 000000000 to 001111111 010000000 to 011111111 CSZA Setting prohibited 100000000 to 10111...

Page 182: ...rite Data 7 6 5 4 3 2 1 0 Bit Symbol X7 X6 X5 X4 X3 X2 X1 X0 Read Write R W Reset State 0 0 0 0 0 0 0 0 Function Specify the bank number for the LOCAL X area Since bank 0 is overlapping with the COMMON area this filed must not be specified as 0 LOCALWX 0898H 15 14 13 12 11 10 9 8 Bit Symbol LXE X8 Read Write R W R W 0899H Reset State 0 0 Function Bank for LOCAL X 0 Disable 1 Enable Specify the ban...

Page 183: ...OMMON area this filed must not be specified as 3 LOCALWZ 089CH 15 14 13 12 11 10 9 8 Bit Symbol LZE Z8 Read Write R W R W 089DH Reset State 0 0 Specify the bank number for the LOCAL Z area Settings of the X8 through X0 bits and their corresponding chip select signals Function Bank for LOCAL Z 0 Disable 1 Enable 000000000 to 001111111 010000000 to 011111111 CSZA Setting prohibited 100000000 to 1011...

Page 184: ...groups while the channels with the odd channel number 1 and 3 are classified into the O group OS and OD groups These registers cannot specify bank numbers for each channel but specifies one bank number for all the channels in the same group The following example shows how to specify bank 1 for storing DMA source addresses in the LOCAL X area and also specify bank 2 for storing DMA destination addr...

Page 185: ... 0 Function Specify the bank number for the LOCAL Y area Since bank 3 is overlapping with the COMMON area this filed must not be specified as 3 LOCALESY 08A2H 15 14 13 12 11 10 9 8 Bit Symbol LYE Read Write R W 08A3H Reset State 0 Function Bank for LOCAL Y 0 Disable 1 Enable LOCAL Z Register for the E group DMA Source 7 6 5 4 3 2 1 0 Bit Symbol Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 Read Write R W Reset State 0 ...

Page 186: ... 0 0 Function Specify the bank number for the LOCAL Y area Since bank 3 is overlapping with the COMMON area this filed must not be specified as 3 LOCALEDY 08AAH 15 14 13 12 11 10 9 8 Bit Symbol LYE Read Write R W 08ABH Reset 0 Function Bank for LOCAL Y 0 Disable 1 Enable LOCAL Z Register for the E group DMA Destination 7 6 5 4 3 2 1 0 Bit Symbol Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 Read Write R W Reset State 0...

Page 187: ... 0 Function Specify the bank number for the LOCAL Y area Since bank 3 is overlapping with the COMMON area this filed must not be specified as 3 LOCALOSY 08B2H 15 14 13 12 11 10 9 8 Bit Symbol LYE Read Write R W 08B3H Reset State 0 Function Bank for LOCAL Y 0 Disable 1 Enable LOCAL Z Register for the O group DMA Source 7 6 5 4 3 2 1 0 Bit Symbol Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 Read Write R W Reset State 0 ...

Page 188: ... 0 0 Function Specify the bank number for the LOCAL Y area Since bank 3 is overlapping with the COMMON area this filed must not be specified as 3 LOCALODY 08BAH 15 14 13 12 11 10 9 8 Bit Symbol LYE 08BBH Read Write R W Reset State 0 Function BANK for LOCAL Y 0 Disable 1 Enable LOCAL Z Register for the O group DMA Destination 7 6 5 4 3 2 1 0 Bit Symbol Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 Read Write R W Reset S...

Page 189: ...nk for program 5 2 ldw localrz 8000H Enable LOCAL Z bank for read data 6 ld p8fc 02H P81 1 CS 7 ld p8fc2 04H P82 9 ld xsp 48000H Stack Pointer 48000H 10 ldw localpy 8000H Bank 0 in LOCAL Y is configured as the program bank for subroutines 11 C000yyH 12 call 400000H Call a subroutine 13 14 15 The instructions No 2 through No 8 configure external pins and the Memory Controller The instruction No 9 s...

Page 190: ...ures Bank 0 of the LOCAL Z area to read data from character ROM The instructions No 18 and No 19 are used to read data from character ROM When the CPU generates the address 800000H the MMU translates it to the physical address 000000H which is then placed onto the external address bus A23 to A0 Since the logical address is within the address range of the CS2 space CSZA for NOR Flash is asserted at...

Page 191: ...Access mode CPU Cycle HDMA Cycle Burst length 1 word 1 word or full page selectable Addressing mode Sequential Sequential CAS latency clock 2 2 Write mode Single Single or burst selectable 4 Access cycles CPU access cycles Read cycle 1 word 4 3 3 3 states minimum Write cycle Single 3 2 2 2 states minimum Data size 1 byte 1 word 1 long word HDMA access cycles Read cycle 1 word 4 3 3 3 states full p...

Page 192: ...nd Interval Setting Register 7 6 5 4 3 2 1 0 Bit symbol STMRD STWR STRP STRCD STRC2 STRC1 STRC0 Read Write R W Reset State 1 1 1 1 1 0 0 TRC SDCISR 0251H Function TMRD 0 1 CLK 1 2 CLK TWR 0 1 CLK 1 2 CLK TRP 0 1 CLK 1 2 CLK TRCD 0 1 CLK 1 2 CLK 000 1 CLK 001 2 CLK 010 3 CLK 011 4 CLK 100 5 CLK 101 6 CLK 110 7 CLK 111 8 CLK SDRAM Refresh Control Register 7 6 5 4 3 2 1 0 Bit symbol SSAE SRS2 SRS1 SR...

Page 193: ...ued Before writing the next command make sure that SCMM2 0 is 000 In the case of the Self Refresh Entry command however SCMM2 0 is not cleared to 000 by execution of this command Thus this register can be used as a flag for checking whether or not Self Refresh is being performed Note 2 The Self Refresh Exit command can only be specified while Self Refresh is being performed SDRAM HDMA Burst Length...

Page 194: ...for each SDRAM access cycle generated by each bus master Table 3 10 1 shows the commands that are issued by the SDRAMC Table 3 10 1 Commands Issued by the SDRAMC Command CKEn 1 CKEn SDxxDQM A10 A15 11 A9 0 SDCS SDRAS SDCAS SDWE Bank Activate H H H RA RA L L H H Precharge All H H H H X L L H L Read H H L L CA L H L H Read with Auto Precharge H H L H CA L H L H Write H H L L CA L H L L Write with Au...

Page 195: ...5 A5 A14 A15 A16 A6 A6 A15 A16 A17 A7 A7 A16 A17 A18 A8 A8 A17 A18 A19 A9 A9 A18 A19 A20 A10 A10 A19 A20 A21 AP A11 A20 A21 A22 A12 A21 A22 A23 A13 A22 A23 EA24 A14 A23 EA24 EA25 A15 EA24 EA25 EA26 Row Address AP Auto Precharge c Burst length When the CPU accesses the SDRAM the burst length is fixed to 1 word read single write The burst length can be selected for SDRAM read and write accesses by H...

Page 196: ... A15 A0 D15 D0 RA Bank Active RA CA n CA n 2 D n Read tRCD 1CLK CAS Latency 2CLK D n 2 CAS Latency 2CLK D n 4 CAS Latency 2CLK 4CLK 3CLK 3CLK Read Read CA n 4 SDCLK SDCKE SDLUDQM SDLLDQM A10 A15 A0 D15 D0 RA Bank Active RA CA n D n Read tRCD 1CLK CAS Latency 2CLK D n 2 4CLK 1CLK D n 4 1CLK Burst Stop D dmy D dmy A10 A15 0 Burst Stop Cycle 2CLK SDCS SDRAS SDCAS SDWE ...

Page 197: ... D15 D0 RA Bank Active RA CA n CA n 2 D n 2 Write tRCD 1CLK 3CLK 2CLK tWR 1CLK D n tWR 1CLK D n 4 tWR 1CLK CA n 4 2CLK Write Write SDCS SDRAS SDCAS SDWE SDCLK SDCKE SDLUDQM SDLLDQM A10 A15 A0 D15 D0 RA Bank Active RA CA n D n 2 Write tRCD 1CLK 2CLK 1CLK D n D n 4 1CLK Burst Stop A10 A15 0 Burst Stop Cycle 2CLK D n 6 D end CA n SDCS SDRAS SDCAS SDWE ...

Page 198: ...nables the SDRAM to be accessed at optimum cycles even if the operation frequency is changed by clock gear Command intervals should be set in the SDCISR register according to the operating frequency of the TMP92CF30 and the AC specifications of the SDRAM The SDCICR register must not be changed while the SDRAM is being accessed The timing waveforms for various cases are shown below a Mode Register ...

Page 199: ...D 2CLK SDCISR STRCD 1 TRC 6CLK SDCISR STRC2 0 101 READ NOP D15 D0 DIN TRCD ACTIVE A15 A0 Row Address Column Address Row Address Non MUX address NOP SDCLK COMMAND NOP ACTIVE NOP NOP TRC TRCD 2CLK SDCISR STRCD 1 TWR 2CLK SDCISR STWR 1 TRP 2CLK SDCISR STRP 1 TRC 6CLK SDCISR STRC2 0 101 WRITE PRECHARG D15 D0 DOUT TRCD TWR ACTIVE A15 A0 Row Address Column Address Row Address Non MUX address NOP TRP ...

Page 200: ...fected The timing waveforms for various cases are shown below a 1 word read the read data shift function disabled SDACR SRCS 0 b 1 word read the read data shift function enabled SDACR SRDS 1 SRDSCK 0 CPU data read SDCLK COMMAND ACTIVE NOP NOP READ NOP D15 D0 DIN1 ACTIVE A15 A0 Row Address ColumnAddress Internal system clock Internal dat bus DIN1 Row Address READ Column Address SDCLK COMMAND ACTIVE...

Page 201: ... degradation in performance as the Bank Active command is needed at every access cycle When SDACR SPRE is set to 0 the Read Write commands are executed without Auto Precharge In this case the SDRAM is not precharged at every access cycle and is always in a bank active state This increases the power consumption of the SDRAM but improves performance as there is no need to issue the Bank Active comma...

Page 202: ...esh as below table for your reference Note2 Take care SDRAM specification and CPU operation speed please Table 3 10 3 System clock speed auto refresh interval SDRCR SRS2 0 Frequency system clock MHz 1 2 3 4 6 8 10 20 30 40 60 80 SRS2 SRS1 SRS0 interval state Time auto refresh interval μs 0 0 0 47 47 0 23 5 15 67 11 75 7 83 5 88 4 70 2 35 1 57 1 18 0 78 0 59 0 0 1 78 78 0 39 0 26 0 19 5 13 0 9 75 7...

Page 203: ...fresh state is exited Note that the Auto Refresh function is also disabled at this time Note 2 The SDRAM cannot be accessed while it is in the Self Refresh state Note 3 To execute the HALT instruction after the Self Refresh Entry command insert at least 10 bytes of NOP or other instructions between the instruction to set SDCMM SCMM2 0 to 101 and the HALT instruction Figure 3 10 7 Self Refresh Cycl...

Page 204: ...10 156 states 011 312 states 100 468 states 101 624 states 110 936 states 111 1248 states Auto Refresh 0 Disable 1 Enable Setting SDRCR SSAE to 1 enables automatic execution of the Self Refresh Exit command in synchronization with HALT release Setting SDRCR SSAE to 0 disables automatic execution of the Self Refresh Exit command in synchronization with HALT release The auto exit function should als...

Page 205: ... CPU operation instruction fetch execution is halted Before executing the initialization sequence appropriate port settings must be made to enable the SDRAM control signals and address signals A0 to A15 After the initialization sequence is completed SDCMM SCMM2 0 is automatically cleared to 000 Figure3 10 9 Initialization Sequence Timing SDCLK SDCKE SDLUDQM SDLLDQM A10 A15 A0 Precharge All Eight A...

Page 206: ...0 A10 A10 A10 A10 A11 BS A11 A11 A11 A11 A12 BS0 BS0 A12 A12 A13 BS1 BS1 BS0 BS0 A14 BS1 BS1 A15 SDCS CS CS CS CS CS SDLUDQM UDQM UDQM UDQM UDQM UDQM SDLLDQM LDQM LDQM LDQM LDQM LDQM SDRAS RAS RAS RAS RAS RAS SDCAS CAS CAS CAS CAS CAS SDWE WE WE WE WE WE SDCKE CKE CKE CKE CKE CKE SDCLK CLK CLK CLK CLK CLK SDACR SMUXW 00 TypeA 00 TypeA 01 TypeB 01 TypeB 10 TypeC Command address pin of SDRAM Figure ...

Page 207: ... 512 bytes Calculation example Transfer time SDRAM read time SRAM write time transfer count SDRAM burst start stop time Precharge time Auto Refresh time Auto Refresh count a Read write time SDRAM read 1 state 2 Internal RAM write 1 state 512 bytes 4 bytes 384 states 1 60 MHz 6 4 μs b Burst start stop time Start TRCD 2CLK 5 states Stop 2 states 7states 60 MHz 0 117 μs c Auto Refresh time Based on t...

Page 208: ... set Therefore to execute the HALT instruction after one of these commands be sure to insert at least 10 bytes of NOP or other instructions 3 Auto Refresh interval setting When SDRAM is used the system clock frequency must be set to satisfy the minimum operation frequency and minimum Auto Refresh interval of the SDRAM to be used In a system in which SDRAM is used and the clock is geared up and dow...

Page 209: ...18 bytes Although the NDFC has two channels channel 0 channel 1 all pins except for Chip Enable are shared between the two channels Only the operation of channel 0 is explained here The NDFC has the following features 1 Controls the NAND Flash memory interface through registers 2 Supports 8 bit and 16 bit NAND Flash memory devices 3 Supports page sizes of 512 bytes and 2048 bytes 4 Supports large ...

Page 210: ...RE ND_ALE ND_CLE ND WE ND_RB DATA_IN 15 0 NAND Flash Controller Channel 0 NDFC0 DATA_OUT 15 0 NDCLE NDALE NDRE NDWE D15 D0 D15 D0 NDR B CE 0 ND Internal Data Bus Reed Solomon ECC Generator Hamming ECC Generator Reed Solomon ECC Calculator Timing Generator Control Register Address Data F F 80 bit ECC Code RS ECC Write ...

Page 211: ... This section explains the operations for accessing the NAND Flash Since no dedicated sequencer is provided for generating commands to the NAND Flash the levels of the NDCLE NDALE and NDCE pins must be controlled by software Figure3 11 2 Basic Timing for Accessing NAND Flash NDCLE NDALE NDCE NDRE NDR B D15 D0 ND0FMCR ALE 0 NDFMCR0 CLE 0 NDFMCR0 ALE 1 NDFMCR0 CLE 1 NDFMCR0 CE0 1 NDWE ...

Page 212: ...erating speed fSYS and the access time of the NAND Flash For details refer to the electrical characteristics The following shows an example of accessing the NAND Flash in 6 clocks by setting NDFMCR0 SPLW1 0 2 and NDFMCR0 SPHW1 0 2 In write cycles the data drive time also becomes longer Figure3 11 3 Read Write Access to NAND Flash FF1234H IN Program 001FF0H FF1238H IN Program OUT NAND Flash Program...

Page 213: ...a 2 The ECC is written to the redundant area in the NAND Flash separately from the valid data Read 1 When data is read from the actual NAND Flash memory the ECC generator in the NDFC simultaneously generates ECC for the read data 2 The ECC for the written data and the ECC for the read data are compared to detect and correct error bits Valid data write to NAND Flash END Data Write Data Read Valid d...

Page 214: ...r every 518 bytes When using Reed Solomon codes error bit detection calculation is supported by hardware and only error bit correction needs to be implemented by software The differences between Hamming codes and Reed Solomon codes are summarized in Table 3 11 1 Table 3 11 1 Differences between Hamming Codes and Reed Solomon Codes Hamming Reed Solomon Maximum number of correctable errors 1 bit 4 a...

Page 215: ...a single bit error exists in the ECC data itself and the error correction process terminates here error not correctable 5 If each pair of bits 0 to 21 of the XOR result is either 01B or 10B it is determined that the error data is correctable and error correction is performed accordingly If the XOR result contains either 00B or 11B it is determined that the error data is not correctable and the err...

Page 216: ...range of 008H to 20DH the actual error address is obtained by subtracting this address from 20 DH If the valid data is processed as 512 byte the actual error address is obtained by subtracting this address from 207H when the error address in the range of 008H to 207H Example 1 NDRSCAn 005H NDRSCDn 04H 00000100B As the error address 005H is in the range of 000H to 007H no correction is needed Altho...

Page 217: ...Reed Solomon operation 0 Encode Write 1 Decode Read Reed Solomon error calculation start 0 1 Start Always read as 0 Reed Solomon ECC generator write control 0 Disable 1 Enable Figure3 11 5 NAND Flash Mode Control 0 Register a ECCRST The ECCRST bit is used for both Hamming and Reed Solomon codes When NDFMCR1 ECCS 0 setting this bit to 1 clears the Hamming ECC in the ECC generator When NDFMCR1 ECCS ...

Page 218: ...usly by DMA transfer After valid data has been read DMA transfer should be stopped once to change the RSECGW bit from 0 to 1 before ECC can be read Note 2 Immediately after ECC is read from the NAND Flash the NAND Flash access operation or error bit calculation cannot be performed for a duration of 20 system clocks fSYS It is necessary to insert 20 NOP instructions or the like g RSESTA The RSESTA ...

Page 219: ...e code is latched so that the ECC generator can generate the ECC for another page without problem while the ECC calculator is calculating the error address and error bit position At this time the ECC generator can perform both encode write and decode read operations When RSECCL is set to 0 the latch is released and the contents of the ECC calculator are updated as the data in the ECC generator is ...

Page 220: ... ended 2 Error found 0100 1111 Calculation in progress Note The STATE3 0 value becomes effective after the calculation has started SEER 1 0 Meaning 00 1 address error 01 2 address error 10 3 address error 11 4 address error Note The SEER1 0 value becomes effective after the calculation has ended a SYSCKE The SYSCKE bit is used for both Hamming and Reed Solomon codes When using the NDFC this bit mu...

Page 221: ...en 0 e INTRDY The INTRDY bit is used for both Hamming and Reed Solomon codes This bit is used to enable or disable the interrupt to be generated when the status of the NDR B pin of the NAND Flash changes from busy 0 to ready 1 The interrupt is enabled when this bit is set to 1 and disabled when 0 f STATE3 0 SEER1 0 The STATE3 0 and SEER1 0 bits are used only for Reed Solomon codes When using Hammi...

Page 222: ...lthough these registers allow both read and write operations no flip flop is incorporated Since write and read operations are performed in different manners it is not possible to read out the data that has been just written Figure3 11 6 NAND Flash Data Registers NDFDTR0 NDFDTR1 Write and read operations to and from the NAND Flash memory are performed by accessing the NDFDTR0 register When you writ...

Page 223: ...1 byte access ld 0x1FF0 a Supported Not supported 2 byte access ld 0x1FF0 wa Supported Supported 4 byte access ld 0x1FF0 xwa Supported Supported Read Access Data Size Example of instruction 8 bit NAND Flash 16 bit NAND Flash 1 byte access ld a 0x1FF0 Supported Not supported 2 byte access ld wa 0x1FF0 Supported Supported 4 byte access ld xwa 0x1FF0 Supported Supported ...

Page 224: ...CCD12 ECCD11 ECCD10 ECCD9 ECCD8 Read Write R Reset State 0 0 0 0 0 0 0 0 08C7H Function NAND Flash ECC Register 15 8 NAND Flash ECC Register 2 7 6 5 4 3 2 1 0 bit Symbol ECCD7 ECCD6 ECCD5 ECCD4 ECCD3 ECCD2 ECCD1 ECCD0 Read Write R Reset State 0 0 0 0 0 0 0 0 Function NAND Flash ECC Register 7 0 NDECCRD2 08C8H 15 14 13 12 11 10 9 8 bit Symbol ECCD15 ECCD14 ECCD13 ECCD12 ECCD11 ECCD10 ECCD9 ECCD8 Re...

Page 225: ...its After ECC calculation has completed in the case of Hamming codes the 16 bit line parity for the first 256 bytes is stored in the NDECCRD0 register the 6 bit column parity for the first 256 bytes in the NDECCRD1 register ECCE7 2 the 16 bit line parity for the second 256 bytes in the NDECCRD2 register and the 6 bit column parity for the second 256 bytes in the NDECCRD3 register ECCD7 2 In this c...

Page 226: ...Register Name Reed Solomon NAND Flash Address NDECCRD0 15 0 Reed Solomon ECC code 79 64 Upper 8 bits 79 72 address 518 Lower 8 bits 71 64 address 519 NDECCRD1 15 0 Reed Solomon ECC code 63 48 Upper 8 bits 63 56 address 520 Upper 8 bits 55 48 address 521 NDECCRD2 15 0 Reed Solomon ECC code 47 32 Upper 8 bits 47 40 address 522 Lower 8 bits 39 32 address 523 NDECCRD3 15 0 Reed Solomon ECC code 31 16 ...

Page 227: ...A8 Read Write R Reset State 0 0 Function NAND Flash Reed Solomon Calculation Result Address Register 9 8 08D5H 7 6 5 4 3 2 1 0 bit Symbol RS2A7 RS2A6 RS2A5 RS2A4 RS2A3 RS2A2 RS2A1 RS2A0 Read Write R Reset State 0 0 0 0 0 0 0 0 Function NAND Flash Reed Solomon Calculation Result Address Register 7 0 NDRSCA2 08D8H 15 14 13 12 11 10 9 8 bit Symbol RS2A9 RS2A8 Read Write R Reset State 0 0 Function NAN...

Page 228: ...et State 0 0 0 0 0 0 0 0 Function NAND Flash Reed Solomon Calculation Result Data Register 7 0 NDRSCD1 08D6H 7 6 5 4 3 2 1 0 bit Symbol RS2D7 RS2D6 RS2D5 RS2D4 RS2D3 RS2D2 RS2D1 RS2D0 Read Write R Reset State 0 0 0 0 0 0 0 0 Function NAND Flash Reed Solomon Calculation Result Data Register 7 0 NDRSCD2 08DAH 7 6 5 4 3 2 1 0 bit Symbol RS3D7 RS3D6 RS3D5 RS3D4 RS3D3 RS3D2 RS3D1 RS3D0 Read Write R Res...

Page 229: ...t disable ldw xxxx ndeccrd0 Read ECC from internal circuit 1 st Read D15 0 LPR15 0 For first 256 bytes ldw xxxx ndeccrd1 Read ECC from internal circuit 2 nd Read D15 0 FFh CPR5 0 11b For first 256 bytes ldw xxxx ndeccrd0 Read ECC from internal circuit 3 rd Read D15 0 LPR15 0 For second 256 bytes ldw xxxx ndeccrd1 Read ECC from internal circuit 4 th Read D15 0 FFh CPR5 0 11b For second 256 bytes Wr...

Page 230: ...le ld ndfdtr0 10h Auto page program command ldw ndfmcr0 2010h WE disable CLE disable Wait setup time from Busy to Ready 1 Flag polling 2 Interrupt Reading status Read Status ldw ndfmcr0 20B0h WE enable CLE enable ld ndfdtr0 70h Status read command ldw ndfmcr0 2010h WE disable CLE disable ld xx ndfdtr0 Status read ...

Page 231: ...dtr0 ECC data read 3 times Generating ECC Reading ECC Read ECC ldw ndfmcr0 2010h ECC circuit disable ldw xxxx ndeccrd0 Read ECC from internal circuit 1 st Read D15 0 LPR15 0 For first 256 bytes ldw xxxx ndeccrd1 Read ECC from internal circuit 2 nd Read D15 0 FFh CPR5 0 11b For first 256 bytes ldw xxxx ndeccrd0 Read ECC from internal circuit 3 rd Read D15 0 LPR15 0 For second 256 bytes ldw xxxx nde...

Page 232: ...s follows ldw ndfmcr0 20B0h WE Enable CLE enable ld ndfdtr0 90h Write ID read command ldw ndfmcr0 20D0h ALE enable CLE disable ld ndfdtr0 00h Write 00 ldw ndfmcr0 2010h WE disable CLE disable ld xx ndfdtr0 Read 1 st ID maker code ld xx ndfdtr0 Read 2 nd ID device code ...

Page 233: ...ALE enable ldw ndfdtr0 00xxh Address write 4 or 5 times ldw ndfmcr0 508Dh Reset ECC code ECCE enable ldw ndfdtr0 xxxxh Data write 259 times 518byte 256 times 512byte Generating ECC Reading ECC Read ECC ldw ndfmcr0 5008h ECC circuit disable ldw ndfmcr0 50A8h WE enable CLE enable ldw ndfdtr0 0080h serial input command ldw ndfmcr0 50C8h ALE enable ldw ndfdtr0 00xxh Address write 4 or 5 times ldw xxxx...

Page 234: ...0F 20Ehex address D15 0 The write operation is repeated four times to write 2112 bytes Executing page program Set auto page program ldw ndfmcr0 50A8h WE enable CLE enable ldw ndfdtr0 0010h Auto page program command ldw ndfmcr0 5008h WE disable CLE disable Wait set up time from Busy to Ready 1 Flag polling 2 Interrupt Note In case of LB type NANDF programming page size is normally each 2112 bytes a...

Page 235: ... decode mode ldw xxxx ndfdtr0 Data read 259 times 518 bytes 256 times 512 byte ldw ndfmcr0 550Ch RSECGW enable ldw xxxx ndfdtr0 Read ECC 5 times 80 bits Wait set up time 20 system clocks 1 Error bit calculation ldw ndfmcr1 0047h Error bit calculation interrupt enable ldw ndfmcr0 560Ch Error bit calculation circuit start Wait set up time Interrupt routine End of calculation for Reed Solomon Error b...

Page 236: ...ows ldw ndfmcr0 50A8h WE enable CLE enable ldw ndfdtr0 0090h Write ID read command ldw ndfmcr0 50C8h ALE enable CLE disable ldw ndfdtr0 0000h Write 00 ldw ndfmcr0 5008h WE disable CLE disable ldw xxxx ndfdtr0 Read 1 st ID maker code ldw xxxx ndfdtr1 Read 2 ndID device code ...

Page 237: ...D Flash memory to be used and the capacity of the board typical 2 kΩ Note 3 The WP Write Protect pin of NAND Flash is not supported When this function is needed prepare it on an external circuit Figure3 11 10 An Example of Connections with NAND Flash NDCLE NDALE NDRE NDWE NDR B D 15 0 CE 0 ND CE 1 ND TMP92CF30 CLE ALE RE WE R B open drain I O 15 0 CE WP NAND Flash 0 CLE ALE RE WE R B open drain I ...

Page 238: ...els The operation mode and timer flip flops are controlled by a 5bytes registers SFRs Special function registers Each of the 4 modules TMRA01 to TMRA67 can be operated independently All modules operate in the same manner hence only the operation of TMRA01 is explained here The contents of this chapter are as follows Table 3 12 1 Registers and Pins for Each Module Module Specification TMRA01 TMRA23...

Page 239: ...φT16 512 256 128 64 32 16 8 4 2 φT1 φT4 φT16 φT256 Run clear Prescaler TA01MOD TA0CLK1 0 Prescaler clock φT0TMR TA01RUN TA0RUN Selector 8 bit timer register TA0REG TA01MOD PWM01 00 TA01MOD TA01M1 0 TMRA0 Interrupt output INTTA0 TMRA0 Interrupt output TA0TRG TA01MOD TA1CLK1 0 TA01RUN TA1RUN TA1FFCR Timer flip flop output TA1OUT TMRA1 Interrupt output INTTA1 Internaldata bus TA01RUN TA0RDE TA01RUN T...

Page 240: ...256 128 64 32 16 8 4 2 φT1 φT4 φT16 φT256 Run clear Prescaler TA23MOD TA2CLK1 0 Prescaler clock φT0TMR TA23RUN TA2RUN Selector 8 bit timer register TA2REG TA23MOD PWM21 20 TA23MOD TA23M1 0 TMRA2 Interrupt output INTTA2 TMRA2 Interrupt output TA2TRG TA23MOD TA3CLK1 0 TA23RUN TA3RUN TA3FFCR Timer flip flop output TA3OUT TMRA3 Interrupt output INTTA3 Internal data bus TA23RUN TA2RDE TA23RUN TA23PRUN ...

Page 241: ... φT16 512 256 128 64 32 16 8 4 2 φT1 φT4 φT16 φT256 Run clear Prescaler TA45MOD TA4CLK1 0 Prescaler clock φT0TMR TA45RUN TA4RUN Selector 8 bit timer register TA4REG TA45MOD PWM41 40 TA45MOD TA45M1 0 TMRA4 Interrupt output INTTA4 TMRA4 Interrupt output TA4TRG TA45MOD TA5CLK1 0 TA45RUN TA5RUN TMRA5 Interrupt output INTTA5 Internal data bus TA45RUN TA4RDE TA45RUN TA45PRUN Selector Internal data bus T...

Page 242: ...2 256 128 64 32 16 8 4 2 φT1 φT4 φT16 φT256 Run clear Prescaler TA67MOD TA6CLK1 0 Prescaler clock φT0TMR TA67RUN TA6RUN Selector 8 bit timer register TA6REG TA67MOD PWM61 60 TA67MOD TA67M1 0 TMRA6 Interrupt output INTTA6 TMRA6 Interrupt output TA6TRG TA67MOD TA7CLK1 0 TA67RUN TA7RUN TA7FFCR Timer flip flop output TA7OUT TMRA7 Interrupt output INTTA7 Internal data bus TA67RUN TA6RDE TA67RUN TA67PRU...

Page 243: ... 2048 fc 32768 000 1 1 fc 32 fc 128 fc 512 fc 8192 001 1 2 fc 64 fc 256 fc 1024 fc 16384 010 1 4 fc 128 fc 512 fc 2048 fc 32768 011 1 8 fc 256 fc 1024 fc 4096 fc 65536 fc 100 1 16 1 1 8 1 2 fc 512 fc 2048 fc 8192 fc 131072 2 Up counters UC0 and UC1 These are 8 bit binary counters which count up the input clock pulses for the clock specified by TA01MOD The input clock for UC0 is selectable and can ...

Page 244: ...rflow occurs in PWM mode or at the start of the PPG cycle in PPG mode Hence the double buffer cannot be used in timer mode When using the double buffer method of renewing timer register is only overflow in PWM mode or frequency agreement in PPG mode A reset initializes TA0RDE to 0 disabling the double buffer To use the double buffer write data to the timer register set TA0RDE to 1 and write the fo...

Page 245: ...riting 00 to these bits inverts the value of TA1FF This is known as software inversion The TA1FF signal is output via the TA1OUT pin When this pin is used as the timer output the timer flip flop should be set beforehand using the port function registers The condition for TA1FF inversion varies with mode as shown below 8 bit interval timer mode UC0 matches TA0REG or UC1 matches TA1REG Select either...

Page 246: ... 1 when read TMRA23 RUN Register 7 6 5 4 3 2 1 0 Bit symbol TA2RDE I2TA23 TA23PRUN TA3RUN TA2RUN Read Write R W R W Reset State 0 0 0 0 0 TMRA23 prescaler Up counter UC3 Up counter UC2 TA23RUN 1108H Function Double buffer 0 Disable 1 Enable In IDLE2 mode 0 Stop 1 Operate 0 Stop and clear 1 Run Count up Note The values of bits 4 to 6 of TA23RUN are 1 when read Figure 3 12 6 Register for TMRA TA0REG...

Page 247: ...en read TMRA67RUN Register 7 6 5 4 3 2 1 0 Bit symbol TA6RDE I2TA67 TA67PRUN TA7RUN TA6RUN Read Write R W R W Reset State 0 0 0 0 0 TMRA67 prescaler Up counter UC7 Up counter UC6 TA67RUN 1118H Function Double buffer 0 Disable 1 Enable In IDLE2 mode 0 Stop 1 Operate 0 Stop and clear 1 Run Count up Note The values of bits 4 to 6 of TA67RUN are 1 when read Figure 3 12 7 Register for TMRA TA4REG doubl...

Page 248: ...φT1 10 φT16 11 φT256 Source clock for TMRA0 00 TA0IN pin 01 φT1 10 φT4 11 φT16 00 TA0IN External input 01 φT1 10 φT4 TA0CLK1 0 11 φT16 TA01MOD TA01M1 0 01 TA01MOD TA01M1 0 01 00 Comparator output from TMRA0 01 φT1 10 φT16 TA1CLK1 0 11 φT256 Overflow output from TMRA0 16 bit timer mode 00 Reserved 01 2 6 Source clock 10 2 7 Source clock PWM01 00 11 2 8 Source clock 00 8 timer 2ch 01 16 bit timer 10...

Page 249: ...φT1 10 φT16 11 φT256 TMRA2 clock for TMRA2 00 TA2IN pin 01 φT1 10 φT4 11 φT16 00 TA2IN External input 01 φT1 10 φT4 TA2CLK1 0 11 φT16 TA23MOD TA23M1 0 01 TA23MOD TA23M1 0 01 00 Comparator output from TMRA2 01 φT1 10 φT16 TA3CLK1 0 11 φT256 Overflow output from TMRA2 16 bit timer mode 00 Reserved 01 2 6 Source clock 10 2 7 Source clock PWM21 20 11 2 8 Source clock 00 8 timer 2ch 01 16 bit timer 10 ...

Page 250: ...φT16 11 φT256 TMRA4 clock for TMRA4 00 low frequency clock 01 φT1 10 φT4 11 φT16 00 low frequency clock fs 01 φT1 10 φT4 TA4CLK1 0 11 φT16 TA45MOD TA45M1 0 01 TA45MOD TA45M1 0 01 00 Comparator output from TMRA4 01 φT1 10 φT16 TA5CLK1 0 11 φT256 Overflow output from TMRA4 16 bit timer mode 00 Reserved 01 2 6 Source clock 10 2 7 Source clock PWM41 40 11 2 8 Source clock 00 8 timer 2ch 01 16 bit time...

Page 251: ...φT16 11 φT256 TMRA6 clock for TMRA6 00 low frequency clock 01 φT1 10 φT4 11 φT16 00 low frequency clock fs 01 φT1 10 φT4 TA6CLK1 0 11 φT16 TA67MOD TA67M1 0 01 TA67MOD TA67M1 0 01 00 Comparator output from TMRA6 01 φT1 10 φT16 TA7CLK1 0 11 φT256 Overflow output from TMRA6 16 bit timer mode 00 Reserved 01 2 6 Source clock 10 2 7 Source clock PWM61 60 11 2 8 Source clock 00 8 timer 2ch 01 16 bit time...

Page 252: ...are TA1FF control for inversion 0 Disable 1 Enable TA1FF inversion select 0 TMRA0 1 TMRA1 0 Inversion by TMRA0 TA1FFIS 1 Inversion by TMRA1 0 Disabled TA1FFIE 1 Enabled 00 Inverts the value of TA1FF Software inversion 01 Sets TA1FF to 1 10 Clears TA1FF to 0 TA1FFC1 0 11 Don t care Note The values of bits 4 to 6 of TA1FFCR are 1 when read Figure 3 12 12 Register for TMRA Control of TA1FF Inversion ...

Page 253: ...are TA3FF control for inversion 0 Disable 1 Enable TA3FF inversion select 0 TMRA2 1 TMRA3 0 Inversion by TMRA2 TA3FFIS 1 Inversion by TMRA3 0 Disabled TA3FFIE 1 Enabled 00 Inverts the value of TA3FF Software inversion 01 Sets TA3FF to 1 10 Clears TA3FF to 0 TA3FFC1 0 11 Don t care Note The values of bits 4 to 6 of TA3FFCR are 1 when read Figure 3 12 13 Register for TMRA Control of TA3FF Inversion ...

Page 254: ...are TA7FF control for inversion 0 Disable 1 Enable TA7FF inversion select 0 TMRA6 1 TMRA7 0 Inversion by TMRA6 TA7FFIS 1 Inversion by TMRA7 0 Disabled TA7FFIE 1 Enabled 00 Inverts the value of TA7FF Software inversion 01 Sets TA7FF to 1 10 Clears TA7FF to 0 TA7FFC1 0 11 Don t care Note The values of bits 4 to 6 of TA7FFCR are 1 when read Figure 3 12 14 Register for TMRA Control of TA7FF Inversion ...

Page 255: ...e W TA2REG 110AH Reset State 0 bit Symbol Read Write W TA3REG 110BH Reset State 0 bit Symbol Read Write W TA4REG 1112H Reset State 0 bit Symbol Read Write W TA5REG 1113H Reset State 0 bit Symbol Read Write W TA6REG 111AH Reset State 0 bit Symbol Read Write W TA7REG 111BH Reset State 0 Note A read modify write operation cannot be performed for All registers Figure 3 12 15 TMRA Registers ...

Page 256: ...INTTA1 interrupt every 20 μs at fSYS 50 MHz set each register as follows Clock state Clcok gear 1 1 Prescaler of clock gear 1 2 MSB LSB 7 6 5 4 3 2 1 0 TA01RUN X X X 0 Stop TMRA1 and clear it to 0 TA01MOD 0 0 X X 0 1 X X Select 8 bit timer mode and select φT1 0 16 μs at fSYS 50 MHz as the input clock TA1REG 0 1 1 1 1 1 0 1 Set TA1REG to 20 μs φT1 125 7DH INTETA1 X 1 0 1 X Enable INTTA1 and set it ...

Page 257: ...2 1 0 TA01RUN X X X 0 Stop TMRA1 and clear it to 0 TA01MOD 0 0 X X 0 1 X X Select 8 bit timer mode and select φT1 0 16 μs at fSYS 50 MHz as the input clock TA1REG 0 0 0 0 1 0 1 0 Set the timer register to 3 2 μs φT1 2 0AH TA1FFCR X X X X 1 0 1 1 Clear TA1FF to 0 and set it to invert on the match detect signal from TMRA1 PM X X X X 0 X PMFC X X X X 1 X Set PM1 to function as the TA1OUT pin TA01RUN ...

Page 258: ...t from TMRA0 is used as the input clock for TMRA1 regardless of the value set in TA01MOD TA01CLK1 0 Table 3 12 2 shows the relationship between the timer Interrupt cycle and the input clock selection Example To generate an INTTA1 interrupt every 0 13 s at fSYS 50 MHz set the timer registers TA0REG and TA1REG as follows Clock state Clcok gear 1 1 Prescaler of clock gear 1 2 If φT16 2 6 μs at fSYS 5...

Page 259: ...A1FF is inverted Example When TA1REG 04H and TA0REG 80H Figure 3 12 18 Timer Output by 16 Bit Timer Mode 3 8 bit PPG Programmable pulse generation output mode Square wave pulses can be generated at any frequency and duty ratio by TMRA0 The output pulses may be active low or active high In this mode TMRA1 cannot be used TMRA0 outputs pulses on the TA1OUT pin Figure 3 12 19 8 Bit PPG Output Waveform...

Page 260: ...will be shifted into TA0REG each time TA1REG matches UC0 Use of the double buffer facilitates the handling of low duty waves when duty is varied Figure 3 12 21 Operation of Register Buffer Note The values that can be set in TAxREG renge from 01h to 00h equivalent to 100h If the maximum value 00h is set the match detect signal goes active when the up counter overfolws 8 bit up counter UC0 Comparato...

Page 261: ...e duty is to be set to 1 4 t 1 4 32 μs 1 4 8 μs 8 μs 0 16 μs 50 Therefore set TA0REG 50 32H 7 6 5 4 3 2 1 0 TA01RUN X X X 0 0 Stop TMRA0 and TMRA1 and clear it to 0 TA01MOD 1 0 X X X X 0 1 Set the 8 bit PPG mode and select φT1 as input clock TA0REG 0 0 0 0 1 0 1 0 Write 32H TA1REG 1 1 0 0 1 0 0 0 Write C8H TA1FFCR X X X X 0 1 1 X Set TA1FF enabling both inversion and the double buffer Writing 10 p...

Page 262: ...ounter UC0 is cleared when 2n counter overflow occurs The following conditions must be satisfied before this PWM mode can be used Value set in TA0REG Value set for 2n counter overflow Value set in TA0REG 0 Figure 3 12 22 8 Bit PWM Waveforms Figure 3 12 23 shows a block diagram representing this mode Figure 3 12 23 Block Diagram of 8 Bit PWM Mode Selector 8 bit up counter UC0 Comparator TA0IN φT1 φ...

Page 263: ...6 0 μs when φT1 0 16 μs set the following value for TAREG 16 0 μs 0 16 μs 100 64H Clock state Clcok gear 1 1 Prescaler of clock gear 1 2 MSB LSB 7 6 5 4 3 2 1 0 TA01RUN X X X 0 Stop TMRA0 and clear it to 0 TA01MOD 1 1 1 0 X X 0 1 Select 8 bit PWM mode cycle 2 7 and select φT1 as the input clock TA0REG 0 1 1 0 0 1 0 0 Write 64H TA1FFCR X X X X 1 0 1 X Clear TA1FF to 0 enable the inversion and doubl...

Page 264: ... fc 16384 fc 65536 fc 262144 fc 010 x4 8192 fc 32768 fc 131072 fc 16384 fc 65536 fc 262144 fc 32768 fc 131072 fc 524288 fc 011 x8 16384 fc 65536 fc 262144 fc 32768 fc 131072 fc 524288 fc 65536 fc 262144 fc 1048576 fc 1 fc 100 x16 1 x8 x2 32768 fc 131072 fc 524288 fc 65536 fc 262144 fc 1048576 fc 131072 fc 524288 fc 2097152 fc 5 Settings for each mode Table 3 12 4 shows the SFR settings for each mo...

Page 265: ...r is controlled by an 11 byte control SFR Each channel TMRB0 TMRB1 operate independently In this section the explanation describes only for TMRB0 because each channel is identical operation except for the difference as follows Table 3 13 1 Difference between TMRB0 and TMRB1 Channel Specification TMRB0 TMRB1 External clock capture trigger input pins TB0IN0 Shared with PP4 TB1IN0 Shared with PP5 Ext...

Page 266: ... register TB0RG1H L TB0MOD TB0CP0I 16 bit comparator CP11 Capture external interrupt input control TB0RUN TB0RUN Caputure register 1 TB0CP1H L Capture register 0 TB0CP0H L Run clear Internal data bus Match detection 16 bit up counter UC10 Count clock from TMRA01 Prescaler clock φT0TMR 32 16 8 4 2 φT1 φT4 φT16 TB0RUN TB0PRUN Internal data bus TB0MOD TB0CLE Intenal data bus Timer flip flop Timer fli...

Page 267: ...ter TB1RG1H L TB1MOD TB1CP0I 16 bit comparator CP13 Capture external interrupt input control TB1RUN TB1RUN Caputure register 1 TB1CP1H L Capture register 0 TB1CP0H L Run clear Internal data bus Match detection 16 bit up counter UC12 Count clock from TMRA01 Prescaler clock φT0TMR 32 16 8 4 2 φT1 φT4 φT16 TB1RUN TB1PRUN Internal data bus TB1MOD TB1CLE Intenal data bus Timer flip flop Interrupt outpu...

Page 268: ... fc 64 fc 256 010 1 4 fc 32 fc 128 fc 512 011 1 8 fc 64 fc 256 fc 1024 100 1 16 0 1 2 fc 128 fc 512 fc 2048 000 1 1 fc 32 fc 128 fc 512 001 1 2 fc 64 fc 256 fc 1024 010 1 4 fc 128 fc 512 fc 2048 011 1 8 fc 256 fc 1024 fc 4096 fc 100 1 16 1 1 8 1 2 fc 512 fc 2048 fc 8192 2 Up counter UC10 UC10 is a 16 bit binary counter which counts up pulses input from the clock specified by TB0MOD TB0CLK1 0 Any o...

Page 269: ... bit data is written in the register buffer regardless of the register buffer to the timer register unexpectedly as explained below For example let us assume that an interrupt occurs when only the lower 8 bits L1 of the register buffer data H1L1 have been written and the interrupt routine includes writes to all 16 bits in the register buffer and a transfer of the data to the timer register In this...

Page 270: ...the value is written to the register buffer 10 only The addresses of the timer registers are as follows Upper 8 bits TB0RG0H Lower 8 bits TB0RG0L TB0RG0H L 1189H 1188H Upper 8 bits TB0RG1H Lower 8 bits TB0RG1L TB0RG1H L 118BH 118AH TMRB0 Upper 8 bits TB1RG0H Lower 8 bits TB1RG0L TB1RG0H L 1199H 1198H Upper 8 bits TB1RG1H Lower 8 bits TB1RG1L TB1RG1H L 119BH 119AH TMRB1 The timer registers are writ...

Page 271: ...lue of the up counter UC10 into TB0CP0H L and TB0CP1H L and generates external interrupt The latch timing of capture register and selection of edge for external interrupt is controlled by TB0MOD TB0CPM1 0 The value in the up counter UC10 can be loaded into a capture register by software Whenever 0 is written to TB0MOD TB0CP0I the current value in the up counter UC10 is loaded into capture register...

Page 272: ... the match detect signal and a setting change via the TB0FFCR register occurs simultaneously the resultant operation varies depending on the situation as shown below If an inversion by the match detect signal and an inversion via the register occur simultaneously the flip flop will be inverted only once If an inversion by the match detect siganl and an attempt to set the flip flop to 1 via the reg...

Page 273: ...p Note 1 4 and 5 of TB0RUN are read as 1 values TMRB1 RUN Register 7 6 5 4 3 2 1 0 Bit symbol TB1RDE I2TB1 TB1PRUN TB1RUN Read Write R W R W R W R W R W Reset State 0 0 0 0 0 TMRB1 prescaler Up counter UC12 TB1RUN 1190H Function Double buffer 0 disable 1 enable Always write 0 In IDLE2 mode 0 Stop 1 Operate 0 Stop and clear 1 Run Count up Note 1 4 and 5 of TB1RUN are read as 1 values Figure 3 13 3 ...

Page 274: ...B0IN0 input 01 φT1 10 φT4 11 φT16 Figure 3 13 4 Register for TMRB TMRB0 source clock 00 TB0IN0 pin input 01 φT1 10 φT4 TB0CLK1 0 11 φT16 Control clearing for up counter UC10 0 Disable TB0CLE 1 Enable clearing by match with TB0RG1H L Capture interrupt timing Capture control INT6 control 00 Disable 01 Capture to TB0CP0H L at rising edge of TB0IN0 INT6 occurs at the rising edge of TB0IN0 10 Capture t...

Page 275: ...B1IN0 input 01 φT1 10 φT4 11 φT16 Control clearing for up counter UC12 0 Disable TB1CLE 1 Enable clearing by match with TB1RG1H L Figure 3 13 5 Register for TMRB TMRB1 source clock 00 TB1IN0 pin input 01 φT1 10 φT4 TB1CLK1 0 11 φT16 Capture interrupt timing Capture control INT7 control 00 Disable 01 Capture to TB1CP0H L at rising edge of TB1IN0 INT7 occurs at the rising edge of TB1IN0 10 Capture t...

Page 276: ... TB0RG0H L Control TB0FF0 00 Invert 01 Set 10 Clear 11 Undefined Always read as 11 Timer flip flop control TB0FF0 00 Invert 01 Set to 11 10 Clear to 00 TB0FF0C1 0 11 Undefined Always read as 11 Figure 3 13 6 Register for TMRB TB0FF0 control Inverted when UC10 value matches the valued in TB0RG0H L 0 Disable trigger TB0E0T1 1 Enable trigger TB0FF0 control Inverted when UC10 value matches the valued ...

Page 277: ...TB0RG1L 118AH Reset State 0 bit Symbol Read Write W TB0RG1H 118BH Reset State 0 bit Symbol Read Write W TB1RG0L 1198H Reset State 0 bit Symbol Read Write W TB1RG0H 1199H Reset State 0 bit Symbol Read Write W TB1RG1L 119AH Reset State 0 bit Symbol Read Write W TB1RG1H 119BH Reset State 0 Note A read modify write operation cannot be performed for All registers Figure 3 13 7 Register for TMRB ...

Page 278: ...are No change 2 16 bit event counter mode In 16 bit timer mode as described in above the timer can be used as an event counter by selecting the external clock TB0IN0 pin input as the input clock Up counter UC10 counts up at the rising edge of TB0IN0 input To read the value of the counter first perform software capture once and read the captured value 7 6 5 4 3 2 1 0 TB0RUN 0 X X X 0 Stop TMRB0 PPC...

Page 279: ...ulse Generation PPG Output Waveforms When the TB0RG0H L double buffer is enabled in this mode the value of register buffer 10 will be shifted into TB0RG0H L at match with TB0RG1H L This feature facilitates the handling of low duty waves Figure 3 13 9 Operation of double buffer Note The values that can be set in TBxRGxH L range from 0001h to 0000h equivalent to 10000h If the maximum value 000h is s...

Page 280: ...he duty and frequency are changed on an INTTB01 interrupt TB0FFCR X X 0 0 1 1 1 0 Set the mode to invert TB0FF0 at the match with TB0RG0H L TB0RG1H L Set TB0FF0 to 0 TB0MOD 0 0 1 0 0 1 Select the internal clock as the input clock and disable 01 10 11 the capture function PPFC 1 X Set PP6 to function as TB0OUT0 TB0RUN 1 0 X X 1 X 1 Start TMRB0 X Don t care No change Selector 16 bit up counter UC10 ...

Page 281: ... time d to TB0RG0H L c d and set the above set value c d plus a one shot pulse width p to TB0RG1H L c d p The TB0FFCR TB0E1T1 TB0E0T1 register should be set 11 and that the TB0FF0 inversion is enabled only when the up counter value matches TB0RG0H L or TB0RG1H L When interrupt INTTB01 occurs this inversion will be disabled after one shot pulse is output The c d and p correspond to c d and p in the...

Page 282: ...H L TB0CP0H L 3ms φT1 TB0RG1H L TB0RG0H L 2ms φT1 TB0FFCR X X 1 1 Enable TB0FF0 inversion when the up counter value matches TB0RG0H L or TB0RG1H L INTETB0 X 1 0 0 X 0 0 0 Enable INTTB01 Setting in INTTB01 routine TB0FFCR X X 0 0 Disable TB0FF0 inversion when the up counter value matches TB0RG0H L or TB0RG1H L INTETB0 X 0 0 0 X 0 0 0 Disable INTTB01 X Don t care No change When delay time is unneces...

Page 283: ...ues in TB0CP0H L and TB0CP1H L when the interrupt INTTA0 or INTTA1 is generated by either 8 bit timer Figure 3 13 13 Frequency Measurement For example if the value for the level 1 width of TA1FF of the 8 bit timer is set to 0 5 s and the difference between TB0CP0H L and TB0CP1H L is 100 the frequency will be 100 0 5 s 200 Hz Note The frequency in this examole is calculated with 50 duty c p c Inver...

Page 284: ...k cycle For example if the internal clock is 0 8 us and the difference between TB0CP0H L and TB0CP1H L is 100 the pulse width will be 100 0 8 μs 80μs Additionally the pulse width which is over the UC10 maximum count time specified by the clock source can be measured by changing software Figure 3 13 14 Pulse Width Measurement Note Only in this pulse width measuring mode TB0MOD TB0CPM1 0 10 external...

Page 285: ...ock diagrams for each channel Each channel is compounded mainly prescaler serial clock generation circuit receiving buffer and control circuit transmission buffer and control circuit Each channel can be used independently Each channel operates in the same fashion except for the following points hence only the operation of channel 0 is explained below Table 3 14 1 Differences between Channels 0 to ...

Page 286: ... 3 4 5 7 Stop Start Bit0 1 2 3 4 5 Parity Stop Start 7 6 6 Bit0 1 2 3 4 5 8 Stop Start Bit0 1 2 3 4 5 Stop Start Bit8 6 6 7 7 Transfer direction Mode 0 I O interface mode Mode 1 7 bit UART mode No parity Parity No parity Parity Mode 2 8 bit UART mode Mode 3 9 bit UART mode When bit8 1 Address Select code is denoted When bit8 0 Data is denoted Wakeup ...

Page 287: ... IOC Receive counter UART only 16 Transmision counter UART only 16 Receive control Transmission control INTRX0 INTTX0 Receive buffer 2 SC0BUF RB8 Error flag SC0CR OERR PERR FERR Serial channel interrupt control TB8 CTS0 TXD0 Transmission buffer SC0BUF RXD0 TXDCLK SC0MOD0 WU fIO SC0MOD0 RXE SCLK0 output SCLK0 input SIOCLK Internal data bus Parity control SC0CR PE EVEN Serial clock generation circui...

Page 288: ...ve counter UART only 16 Transmision counter UART only 16 Receive control Transmission control INTRX1 INTTX1 Receive buffer 2 SC0BUF RB8 Error flag SC1CR OERR PERR FERR Serial channel interrupt control TB8 CTS1 TXD1 Transmission buffer SC1BUF RXD1 TXDCLK SC1MOD0 WU fIO SC1MOD0 RXE SCLK1 output SCLK1 input SIOCLK Internal data bus Parity control SC1CR PE EVEN Serial clock generation circuit BR1CR BR...

Page 289: ...nal circuit and external port Note1 Figure 3 14 4 shows connection image The circuit compounds and a setting procedure Refer to section of Port Note2 When shifting extrernal port shift port after stop internal circuits completely fIO SCLK0 input φT0 Internal data bus SCLK0 output RXD0 input TXD0 CTS0 fIO SCLK1 input φT0 SCLK1 output RXD1 input TXD1 CTS1 INTRX0 to INTC INTTX0 to INTC INTRX1 to INTC...

Page 290: ...d rate generator Table 3 14 2 Prescaler Clock Resolution to Baud Rate Generator Baud Rate Generator input clock SIO Prescaler BR0CR BR0CK1 0 Clock gear SYSCR1 GEAR2 0 φT0 1 1 φT2 1 4 φT8 1 16 φT32 1 64 000 1 1 fc 4 fc 16 fc 64 fc 256 001 1 2 fc 8 fc 32 fc 128 fc 512 010 1 4 fc 16 fc 64 fc 256 fc 1024 011 1 8 fc 32 fc 128 fc 512 fc 2048 fc 100 1 16 1 4 fc 64 fc 256 fc 1024 fc 4096 The baud rate gen...

Page 291: ...ings BR0ADD BR0K3 0 are ignored The baud rate generator divides the selected prescaler clock by N which is set in BR0CK BR0S3 0 N 1 2 3 16 When BR0CR BR0ADDE 1 The N 16 K 16 division function is enabled The baud rate generator divides the selected prescaler clock by N 16 K 16 using the value of N set in BR0CR BR0S3 0 N 2 3 15 and the value of K set in BR0ADD BR0K3 0 K 1 2 3 15 Note If N 1 or N 16 ...

Page 292: ...15 9744 MHz the input clock is φT2 the frequency divider N BR0CR BR0S3 0 6 K BR0ADD BR0K3 0 8 and BR0CR BR0ADDE 1 the baud rate in UART Mode is as follows Clock state Clock gear 1 1 Input clock of baud rate generator Baud Rate Frequency divider for baud rate generator 16 fC 16 16 8 6 16 16 8 15 9744 10 6 16 6 16 16 9600 bps Table 3 14 3 show examples of UART Mode transfer rates Additionally the ex...

Page 293: ... 200 58 9824 2 460 800 115 200 28 800 7 200 3 307 200 76 800 19 200 4 800 5 184 320 46 080 11 520 2 880 6 153 600 38 400 9 600 2 400 8 115 200 28 800 7 200 1 800 C 76 800 19 200 4 800 1 200 F 61 440 15 360 3 840 0 960 73 728 1 1152 000 288 000 72 000 18 000 3 384 000 96 000 24 000 6 000 6 192 000 48 000 12 000 3 000 A 115 200 28 800 7 200 1 800 C 96 000 24 000 6 000 1 500 F 76 800 19 200 4 800 1 2...

Page 294: ...ata each data bit is sampled three times on the 7th 8th and 9th clock cycles The value of the data bit is determined from these three samples using the majority rule For example if the data bit is sampled respectively as 1 0 and 1 on 7th 8th and 9th clock cycles the received data bit is taken to be 1 A data bit sampled as 0 0 and 1 is taken to be 0 5 Receiving control In I O Interface Mode In SCLK...

Page 295: ...controller is enabled by setting SC0MOD0 WU to 1 in this mode INTRX0 interrupts occur only when the value of SC0CR RB8 is 1 SIO interrupt mode is selectable by the register SIMC Note1 The double buffer structure does not support SC0CR RB8 Note2 If the CPU reads receive buffer 2 while data is being transferred from receive buffer 1 to receive buffer 2 the data may not be read properly To avoid this...

Page 296: ... shift clock which is output on the SCLK0 pin according to the SC0CR SCLKS setting In SCLK Input Mode with the setting SC0CR IOC 1 the data in the Transmission Buffer is output one bit at a time on the TXD0 pin on the rising or falling edge of the SCLK0 input according to the SC0CR SCLKS setting In UART Mode When transmission data sent from the CPU is written to the Transmission Buffer transmissio...

Page 297: ...in a handshake function can be easily configured by setting any port assigned to be the RTS function The RTS should be output high to request send data halt after data receive is completed by software in the RXD interrupt routine Figure 3 14 6 Handshake function Note 1 If the 0 CTS signal goes High during transmission no more data will be sent after completion of the current transmission Note 2 Tr...

Page 298: ...itten to the transmission buffer In the case of receiving data is shifted into receiving buffer 1 and the parity is added after the data has been transferred to receiving buffer 2 SC0BUF and then compared with SC0BUF RB7 in 7 bit UART mode or with SC0CR RB8 in 8 bit UART mode If they are not equal a parity error is generated and the SC0CR PERR flag is set 12 Error flags Three error flags are provi...

Page 299: ...t Center of stop bit Center of stop bit Parity error timing Center of last bit parity bit Center of stop bit Overrun error timing Center of last bit bit 8 Center of last bit parity bit Center of stop bit Note In 9 Bit and 8 Bit Parity Modes interrupts coincide with the ninth bit pulse Thus when servicing the interrupt it is necessary to wait for a 1 bit period to allow the stop bit to be transferr...

Page 300: ...1 External clock SCLK0 input Figure 3 14 8 Serial Mode Control Register channel 0 SC0MOD0 Serial transmission clock source UART 00 TMRA0 match detect signal 01 Baud rate generator 10 Internal clock fIO 11 External clock SCLK0 input Note The clock selection for the I O interface mode is controlled by the serial bontrol register SC0CR Serial Transmission Mode 00 I O Interface Mode 01 7 bit mode 10 8...

Page 301: ... is possible to use only TMRA0 same with timer of SIO0 Timer differ with SIO0 cannot use Please be careful Figure 3 14 9 Serial Mode Control Register channel 1 SC1MOD0 Serial transmission clock source UART 00 TMRA0 match detect signal 01 Baud rate generator 10 Internal clock fIO 11 External clock SCLK1 input Note The clock selection for the I O interface mode is controlled by the serial bontrol re...

Page 302: ...K0 pin input Note As all error flags are cleared after reading do not test only a single bit with a bit testing instruction Figure 3 14 10 Serial Control Register channel 0 SC0CR I O interface input clock selection Framing Error flag Parity Error flag Overrun Error flag 0 Transmits and receives data on rising edge of SCLK0 1 Transmits and receives data on falling edge SCLK0 Edge selection for SCLK...

Page 303: ...K1 pin input Note As all error flags are cleared after reading do not test only a single bit with a bit testing instruction Figure 3 14 11 Serial Control Register channel 1 SC1CR I O interface input clock selection Framing Error flag Parity Error flag Overrun Error flag 0 Transmits and receives data on rising edge of SCLK1 1 Transmits and receives data on falling edge SCLK1 Edge selection for SCLK...

Page 304: ... N 15 0000 N 16 0000 Disable Disable 0001 K 1 to 1111 K 15 Disable Divided by N 16 K 16 Divided by N Note1 Availability of 16 K 16 division function N UART mode I O mode 2 to 15 1 16 The baud rate generator can be set to 1 in UART mode only when the 16 K 16 division function is not used Do not use in I O interface mode Note2 Set BR0CR BR0ADDE to 1 after setting K K 1 to 15 to BR0ADD BR0K3 0 when t...

Page 305: ... N 15 0000 N 16 0000 Disable Disable 0001 K 1 to 1111 K 15 Disable Divided by N 16 K 16 Divided by N Note1 Availability of 16 K 16 division function N UART mode I O mode 2 to 15 1 16 The baud rate generator can be set to 1 in UART mode only when the 16 K 16 division function is not used Do not use in I O interface mode Note2 Set BR1CR BR1ADDE to 1 after setting K K 1 to 15 to BR1ADD BR1K3 0 when t...

Page 306: ...05H Function IDLE2 0 Stop 1 Run duplex 0 half 1 full Figure 3 14 15 Serial Mode Control Register 1 channel 0 SC0MOD1 7 6 5 4 3 2 1 0 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0 Transmission SC1BUF 1208H 7 6 5 4 3 2 1 0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 Receiving Note Prohibit read modify write for SC1BUF Figure 3 14 16 Serial Transmission Receiving Buffer Registers channel 1 SC1BUF 7 6 5 4 3 2 1 0 Bit symbol I2...

Page 307: ... Figure 3 14 18 SCLK Output Mode connection example Figure 3 14 19 Example of SCLK Input Mode Connection Output extension TC74HC595 or equivalent A B SI C D SCK E F RCK G H TXD SCLK Port Shift register TMP92CF30 Input extension TC74HC165 or equivalent A B QH C D CLOCK E F S L G H RXD SCLK Port Shift register TMP92CF30 Output extension TC74HC595 or equivalent A B SI C D SCK E F RCK G H TXD SCLK Por...

Page 308: ...output on the TXD0 pin when the SCLK0 input becomes active after the data has been written to the Transmission Buffer by the CPU When all data is output INTES0 ITX0C will be set to generate INTTX0 interrupt Figure 3 14 21 Transmitting Operation in I O Interface Mode SCLK0 Input Mode TXD0 ITX0C INTTX0 interrupt request SCLK0 output SCLKS 0 rising edge mode Timing of transmited data writing Bit0 Bit...

Page 309: ... is shifted to Receiving Buffer 1 when the SCLK input goes active The SCLK input goes active when the Receive Interrupt flag INTES0 IRX0C is cleared as the received data is read When 8 bit data is received the data is shifted to Receiving Buffer 2 SC0BUF following the timing shown below and INTES0 IRX0C is set to 1 again causing an INTRX0 interrupt to be generated Figure 3 14 23 Receiving Operatio...

Page 310: ... rate 9600 bps fSYS 2 4576 MHz Main routine 7 6 5 4 3 2 1 0 INTES0 X 0 0 1 X 0 0 0 Set the INTTX0 level to 1 Set the INTRX0 level to 0 P9CR X X X X X 1 0 1 P9FC X X X 1 X 1 Set P90 P91 and P92 to function as the TXD0 RXD0 and SCLK0 pins respectively SC0MOD0 0 0 Select I O interface mode SC0MOD1 1 X X X X X X Select full duplex mode SC0CR 0 0 SCLK0 output mode select rising edge BR0CR 0 0 0 1 1 0 0...

Page 311: ...ode SC0CR 1 1 Add even parity BR0CR 0 0 1 0 1 0 0 0 Set the transfer rate to 2400 bps INTES0 X 1 0 0 X 0 0 0 Enable the INTTX0 interrupt and set it to interrupt level 4 SC0BUF Set data for transmission X Don t care No change 3 Mode 2 8 Bit UART Mode 8 Bit UART Mode is selected by setting SC0MOD0 SM1 0 to 10 In this mode a parity bit can be added use of a parity bit is enabled or disabled by the se...

Page 312: ...UART Mode 9 Bit UART Mode is selected by setting SC0MOD0 SM1 0 to 11 In this mode a parity bit cannot be added In the case of transmission the MSB 9th bit is written to SC0MOD0 TB8 In the case of receiving it is stored in SC0CR RB8 When the buffer is written or read TB8 or RB8 is read or written first before the rest of the SC0BUF data Wake up function In 9 Bit UART Mode the wake up function for s...

Page 313: ...ntroller whose code matches clears its WU bit to 0 5 The master controller transmits data to the specified slave controller the controller whose SC0MOD0 WU bit has been cleared to 0 The MSB bit 8 of the data TB8 is cleared to 0 6 The other slave controllers whose WU bits remain at 1 ignore the received data because their MSBs bit 8 or RB8 are set to 0 disabling INTRX0 interrupts The slave controll...

Page 314: ...n Mode using fIO as the transfer clock Interrupt routine INTRX0 Acc SC0BUF if Acc Select code Then SC0MOD0 0 Clear WU to 0 Main routine P9CR X X X X X 0 1 P9FC X X X X 1 Set P90 and P91 to function as the TXD0 and RXD0 pins respectively INTES0 X 1 0 0 X 1 0 1 Enable the INTTX0 interrupt and set it to Interrupt Level 4 Enable the INTRX0 interrupt and set it to Interrupt Level 5 SC0MOD0 1 0 1 0 1 1 ...

Page 315: ...modem outputs 0 Figure 3 14 26 Transmission example 2 Modulation of the receive data When the receive data has an effective pulse width of pulse 1 the modem outputs 0 to SIO0 Otherwise the modem outputs 1 to SIO0 The effective pulse width is selected by SIR0CR SIR0WD3 0 Figure 3 14 27 Receiving example 3 Data format The data format is fixed as follows Data length 8 bit Parity bits none Stop bits 1...

Page 316: ...ZI 0 87 1 41 μs 19 53 μs 22 13 μs 19 2 kbps RZI 0 87 1 41 μs 9 77 μs 11 07 μs 38 4 kbps RZI 0 87 1 41 μs 4 88 μs 5 96 μs 57 6 kbps RZI 0 87 1 41 μs 3 26 μs 4 34 μs 115 2 kbps RZI 0 87 1 41 μs 1 63 μs 2 23 μs The infra red pulse width is specified either baud rate T 3 16 or 1 6 μs 1 6 μs is equal to 3 16 pulse width when baud rate is 115 2 kbps The TMP92CF30 has a function which can select the puls...

Page 317: ...dth 2x value 1 100ns 0000 Cannot be set 0001 Equal or more than 4x 100ns to 1110 Equal or more than 30x 100ns 1111 Can not be set Receive recovery operation 0 Disable receiving operation Received data is ignored 1 Enabled receiving operation Transmit modulation operation 0 Disabled transmission operation Input from SIO is ignored 1 Enabled transmission operation Select transmit pulse width 0 3 16 ...

Page 318: ...x value 1 100ns x 1 fSYS 0000 Cannot be set 0001 Equal or more than 4x 100ns to 1110 Equal or more than 30x 100ns 1111 Can not be set Receive recovery operation 0 Disable receiving operation Received data is ignored 1 Enabled receiving operation Transmit modulation operation 0 Disabled transmission operation Input from SIO is ignored 1 Enabled transmission operation Select transmit pulse width 0 3...

Page 319: ...R PV7C PV6C PVFC PV7F PV6F I 2 C bus mode 11 11 11 3 15 1 Configuration Figure 3 15 1 Serial bus interface SBI SIO clock control Divider I 2 C bus clock sync control SBICR2 SBISR SCL SCK Input output control SO SI SDA I2CAR SBIDBR SBICR0 1 SBIBR0 Shift register Transfer control circuit Noise canceller fSYS 4 Noise canceller I 2 C bus data control SIO data control INTSBI interrupt request PV6 SDA P...

Page 320: ... SBIBR0 3 15 3 The Data Formats in the I 2 C Bus Mode The data formats in the I2C bus mode is shown below a Addressing format b Addressing format with restart c Free data format data transferred from master device to slave device Figure 3 15 2 Data format in the I2 C bus mode S Slave address R W Data A C K A C K Data A C K P 8 bits 1 1 to 8 bits 1 1 to 8 bits 1 1 1 or more S Slave address R W Data...

Page 321: ... bus mode Serial Bus Interface Control Register 0 7 6 5 4 3 2 1 0 Bit symbol SBIEN Read Write R W R Reset State 0 0 0 0 0 0 0 0 SBICR0 1247H A read modify write operation cannot be performed Function SBI operation 0 disable 1 enable Always read 0 SBIEN When using SBI SBIEN should be set 1 SBI operation enable before setting each register of SBI module Figure 3 15 3 Registers for the I2 C bus mode ...

Page 322: ...MON at read 0 During software reset 1 Initial Data Acknowledge mode specification 0 Not generate clock pulse for acknowledge signal 1 Generate clock pulse for acknowledge signal Number of bits transferred ACK 0 ACK 1 BC2 0 Number of clock pulses Bits Number of clock pulses Bits 000 001 010 011 100 101 110 111 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 9 2 3 4 5 6 7 8 8 1 2 3 4 5 6 7 Note1 For the frequency o...

Page 323: ...2 00 Port mode 01 Reserved 10 I 2 C Bus mode 11 Reserved Software reset generate write 10 and 01 then an internal reset signal is generated Serial bus interface operating mode selection Note2 00 Port Mode Serial Bus Interface output disabled 01 Reserved 10 I 2 C Bus Mode 11 Reserved Note 1 Reading this register functions as SBISR register Note 2 Switch a mode to port mode after confirming that the...

Page 324: ... match detection monitor 0 Undetected 1 Detected GENERAL CALL detection monitor 0 Undetected 1 Detected Last received bit monitor 0 0 1 1 Last received bit monitor 0 Last received bit was 0 1 Last received bit was 1 GENERAL CALL detection monitor 0 Undetected 1 GENERAL CALL detected Slave address match detection monitor 0 Slave address don t match or Undetected 1 Slave address match or GENERAL CAL...

Page 325: ...art from the MSB bit 7 Receiving data is placed from LSB bit0 Note2 SBIDBR can t be read the written data because of it has buffer for writing and buffer for reading individually Therefore Read modify write instruction e g BIT instruction is prohibitted I2 C Bus Address Register 7 6 5 4 3 2 1 0 Bit symbol SA6 SA5 SA4 SA3 SA2 SA1 SA0 ALS I2CAR 1242H Read Write R W Reset State 0 0 0 0 0 0 0 0 A read...

Page 326: ...e TMP92CF30 does not generate a clock pulse for the Acknowledge signal when operating in the Master Mode 2 Number of transfer bits The SBICR1 BC2 0 is used to select a number of bits for next transmitting and receiving data Since the BC2 0 is cleared to 000 as a start condition a slave address and direction bit transmission are executed in 8 bits Other than these the BC2 0 retains a specified valu...

Page 327: ... the High level Since Master B holds the SCL line of the bus at the Low level Master A wait for counting high level width of an own clock pulse After Master B finishes counting low level width of an own clock pulse at point c and Master A detects the SCL line of the bus at the High level and starts counting High level of an own clock pulse The clock pulse on the bus is determined by the master dev...

Page 328: ...the I2C bus is detected or arbitration is lost 7 Start Stop condition generation When the SBISR BB is 0 slave address and direction bit which are set to SBIDBR are output on a bus after generating a start condition by writing 1 to the SBICR2 MST TRX BB PIN It is necessary to set transmitted data to the data buffer register SBIDBR and set 1 to ACK beforehand Figure 3 15 10 Start condition generatio...

Page 329: ...ore than one master device can exist simultaneously on the bus in I2C Bus Mode a bus arbitration procedure has been implemented in order to guarantee the integrity of transferred data In case set start condition bit with bus is busy start condition is not output on SCL and SDA pin but arbitration lost is generated Data on the SDA line is used for I2C bus arbitration The following shows an example ...

Page 330: ...en I2CAR ALS 1 SBISR AAS is set to 1 after the first word of data has been received SBISR AAS is cleared to 0 when data is written to or read from the data buffer register SBIDBR 12 GENERAL CALL detection monitor SBISR AD0 is set to 1 in Slave Mode when a GENERAL CALL is received all 8 bit received data is 0 after a start condition SBISR AD0 is cleared to 0 when a start condition or stop condition...

Page 331: ... Buffer Register SBIDBR The received data can be read and transferred data can be written by reading or writing the SBIDBR In the master mode after the start condition is generated the slave address and the direction bit are set in this register 16 I2CBUS Address Register I2CAR I2CAR SA6 0 is used to set the slave address when the TMP92CF30 functions as a slave device The slave address output from...

Page 332: ...transmitted to the SBIDBR When SBICR2 BB 0 the start condition are generated by writing 1111 to SBICR2 MST TRX BB PIN Subsequently to the start condition nine clocks are output from the SCL pin While eight clocks are output the slave address and the direction bit which are set to the SBIDBR At the 9th clock the SDA line is released and the acknowledge signal is received from the slave device An IN...

Page 333: ...ress set in I2CAR is received the SDA line is pulled down to the Low level at the 9th clock and the acknowledge signal is output An INTSBI interrupt request occurs on the falling edge of the 9th clock The PIN is cleared to 0 In Slave Mode the SCL line is pulled down to the Low level while the PIN 0 Figure 3 15 14 Start condition generation and slave address transfer 1 2 3 4 5 6 7 8 9 A6 A5 A4 A3 A...

Page 334: ... a serial clock pulse is generated for transferring a new 1 word of data from the SCL pin and then the 1 word data is transmitted After the data is transmitted an INTSBI interrupt request occurs The PIN becomes 0 and the SCL line is pulled down to the Low level If the data to be transferred is more than one word in length repeat the procedure from the LRB checking above INTSBI interrupt if MST 0 T...

Page 335: ...The last data word does not generate a clock pulse as the Acknowledge signal After the data has been transmitted and an interrupt request has been generated set BC2 0 to 001 and read the data The TMP92CF30 generates a clock pulse for a 1 bit data transfer Since the master device is a receiver the SDA line on the bus remains High The transmitter interprets the High signal as an ACK signal The recei...

Page 336: ...R Load the data of 1st to N 2 th End of interrupt INTSBI interrupt N 1 th Receive data 7 6 5 4 3 2 1 0 SBICR1 X X X 0 0 X X X Not generate acknowledge signal Reg SBIDBR Load the data of N 1 th End of interrupt INTSBI interrupt Nth Receive data 7 6 5 4 3 2 1 0 SBICR1 0 0 1 0 0 X X X Generate the clock for 1bit transmit Reg SBIDBR Receive the data of Nth End of interrupt INTSBI interrupt After recei...

Page 337: ...ord data transfer terminates after losing arbitration When an INTSBI interrupt request occurs the PIN is cleared to 0 and the SCL pin is pulled down to the Low level Either reading writing from to the SBIDBR or setting the PIN to 1 will release the SCL pin after taking tLOW time Check the SBISR AL TRX AAS and AD0 and implements processes according to conditions listed in the next table Example In ...

Page 338: ...en clear TRX to 0 to release the bus If LRB is cleared to 0 set BC2 0 to the number of bits in a word and write the transmitted data to SBIDBR since the receiver requests next data 1 1 0 The TMP92CF30 loses arbitration when transmitting a slave address and receives a slave address or GENERAL CALL for which the value of the direction bit sent from another master is 0 1 0 0 The TMP92CF30 loses arbit...

Page 339: ...s been pulled Low by another device the TMP92CF30 generates a stop condition when the other device has released the SCL line and SDA pin rising 7 6 5 4 3 2 1 0 SBICR2 1 1 0 1 1 0 0 0 Generate stop condition Figure 3 15 18 Stop condition generation Single master Figure 3 15 19 Stop condition generation Multi master SCL pin SDA Pin PIN BB Read Stop condition 1 MST 1 TRX 0 BB 1 PIN Internal SCL Inter...

Page 340: ...es After confirming that the bus remains in a free state generate a start condition using the procedure described in 2 In order to satisfy the set up time requirements when restarting take at least 4 7 μs of waiting time by software from the time of restarting to confirm that the bus is free until the time to generate the start condition 7 6 5 4 3 2 1 0 SBICR2 0 0 0 1 1 0 0 0 Release the bus if SB...

Page 341: ...FOs Endpoint 2 BULK in 64 bytes 2 FIFOs Endpoint 3 Interrupt in 8 bytes 1 FIFO 5 Built in DPLL which generates sampling clock for receive data 6 Detecting and generating SOP EOP RESUME RESET and TIMEOUT 7 Encoding and decoding NRZI data 8 Inserting and discarding stuffed bit 9 Detecting and checking CRC 10 Generating and decoding packet ID 11 Built in power management function 12 Dual packet mode ...

Page 342: ...M and PWM request controller descriptor RAM and 4 endpoint FIFO details given in Section 3 16 3 below 3 USB transceiver Figure 3 16 1 UDC Block Diagram Descriptor RAM 384 bytes Request controller Endpoint 0 FIFO 64 bytes 1 Endpoint 1 FIFO 64 bytes 2 Endpoint 2 FIFO 64 bytes 2 Endpoint 3 FIFO 8 bytes 1 PWM DPLL SIE IFM I F FIFO manager 900 H1 CPU interface USB transceiver UDC core ADDRESS RD WR D U...

Page 343: ...o control the pull down resistor which determines the level Recommended value R4 10kΩ R5 10kΩ The example shows use of the connector detection method by using VBUS 5V voltage Note Where waveform rise is solw buffering of wabeform is recommended Recommended value R6 60kΩ R7 100kΩ VBUS current consumption when suspended is 500μA 4 Connection of 10MHz oscillator to X1 X2 or input 48MHz clock to X1USB...

Page 344: ...ndard set pull down D pin and D signal at USB_HOST side Recommended value R8 15kΩ R9 15kΩ Note The above connections and resistor values etc are given as examples only Operation is not guaranteed Please confirm the latest USB standar specifications and operations on your system ...

Page 345: ...USB interrupt control USBINTFR1 USB interrupt flag register 1 USBINTFR2 USB interrupt flag register 2 USBINTFR3 USB interrupt flag register 3 USBINTFR4 USB interrupt flag register 4 USBINTMR1 USB interrupt mask register 1 USBINTMR2 USB interrupt mask register 2 USBINTMR3 USB interrupt mask register 3 USBINTMR4 USB interrupt mask register 4 Table 3 16 1 900 H1 CPU I F SFR Address Read Write SFR Sym...

Page 346: ...ote wakeup function is needed first check Current_Config REMOTE WAKEUP If REMOTE WAKEUP 1 meaning SUSPEND status write 1 and 0 to WAKEUP This will initiate the remote wakeup function If REMOTE WAKEUP 0 or EP0 1 2 3_STATUS SUSPEND 0 do not write 1 to WAKEUP SPEED Bit1 1 Full speed 12 MHz 0 Reserved This bit selects USB speed Always set to 1 USBCLKE Bit0 0 Disable USB clock 1 Enable USB clock This b...

Page 347: ... is not set because interrupt souce changes 1 0 C The flag register is set because mask register 0 and interrupt souce changes 0 1 D The flag register is reset to 0 by writing 0 to flag register Note 1 The INTUSB generated number and bit number which is set to flag register are not always equal In the INTUSB interrupt routine clear FLAG register USBINTFRn after checking it The interrupt request fl...

Page 348: ...t interrupt This is set to 1 when the UDC started to receive a USB reset signal from a USB host An application program has to initialize the whole UDC with this interrupt INT_URST_END Bit6 This is the flag register for INT_URST_END USB reset end interrupt This is set to 1 when the UDC receives a USB reset end signal from a USB host INT_SUS Bit5 This is the flag register for INT_SUS suspend interru...

Page 349: ...R W R W R W Reset State 0 0 0 0 USBINTFR3 07F2H Prohibit to read modify write Function When read 0 Not generate interrupt 1 Generate interrupt When write 0 Clear flag 1 Note The above interrupt can release Halt state from IDLE2 mode IDLE1 and STOP mode cannot be released EPx_FULL_A B When transmitting This is set to 1 when CPU full write data to FIFO_A B When receiving This is set to 1 when UDC fu...

Page 350: ...data phase for Control transfer type interrupt This is set to 1 when the UDC receives data of the data phase for Control transfer type If this interrupt occurs during Control write transfer data reading from FIFO is needed If this interrupt occurs during Control read transfer transmission data writing to FIFO is needed In some cases the host may not assert ACK of the last packet in the data stage ...

Page 351: ...his is set to 1 when the USB host changes to status stage at the Control read transfer This interrupt is needed if data length is less than wLength specified by the host INT_EPxN Bit3 2 1 This is the flag register for INT_EPxN NAK acknowledge to the USB host interrupt This is set to 1 when the Endpoint1 2 and 3 transmit NAK ...

Page 352: ...masked When write 0 Clear flag 1 MSK_URST_STR Bit7 This is the mask register for USBINTFR1 INT_URST_STR MSK_URST_END Bit6 This is the mask register for USBINTFR1 INT_URST_END MSK_SUS Bit5 This is the mask register for USBINTFR1 INT_SUS MSK_RESUME Bit4 This is the mask register for USBINTFR1 INT_RESUME MSK_CLKSTOP Bit3 This is the mask register for USBINTFR1 INT_CLKSTOP MSK_CLKON Bit2 This is the m...

Page 353: ...NTMR2 07F5H Function When read 0 not masked 1 masked When write 0 Clear flag 1 EP1 2_MSK_FA FB EA EB This is the mask register for USBINTFR2 EPx_FULL_A B or EPx_Empty_A B 7 6 5 4 3 2 1 0 bit Symbol EP3_MSK_FA EP3_MSK_EA Read Write R W R W Reset State 1 1 USBINTMR3 07F6H Function When read 0 not masked 1 masked When write 0 Clear flag 1 EP3_MSK_FA FB EA EB This is the mask register for USBINTFR3 EP...

Page 354: ...te 0 Clear flag 1 MSK_SETUP Bit7 This is the mask register for USBINTFR4 INT_SETUP MSK_EP0 Bit6 This is the mask register for USBINTFR4 INT_EP0 MSK_STAS Bit5 This is the mask register for USBINTFR4 INT_STAS MSK_STASN Bit4 This is the mask register for USBINTFR4 INT_STASN MSK_EP1N Bit3 This is the mask register for USBINTFR4 INT_EP1N MSK_EP2N Bit2 This is the mask register for USBINTFR4 INT_EP2N MS...

Page 355: ...urrent_Config register USB_STATE register StandardRequest register Request register EPx_STATUS register d Setup EPx_BCS register EPx_SINGLE register Standard Request Mode register Request Mode register Descriptor RAM register PortStatus register e Control EPx_MODE register EOP register COMMAND register INT_ Control register Setup Received register USBREADY register f Others ADDRESS register DATASE...

Page 356: ...rved 0789H R W EP1_MODE 078AH R W EP2_MODE 078BH R W EP3_MODE 078CH R W EP4_MODE 078DH R W EP5_MODE 078EH R W EP6_MODE 078FH R W EP7_MODE 0790H R EP0_STATUS 0791H R EP1_STATUS 0792H R EP2_STATUS 0793H R EP3_STATUS 0794H R EP4_STATUS 0795H R EP5_STATUS 0796H R EP6_STATUS 0797H R EP7_STATUS 0798H R EP0_SIZE_L_A 0799H R EP1_SIZE_L_A 079AH R EP2_SIZE_L_A 079BH R EP3_SIZE_L_A 079CH R EP4_SIZE_L_A 079DH...

Page 357: ...e 07C1H R bRequest 07C2H R wValue_L 07C3H R wValue_H 07C4H R wIndex_L 07C5H R wIndex_H 07C6H R wLength_L 07C7H R wLength_H 07C8H W Setup Received 07C9H R Current_Config 07CAH R Standard Request 07CBH R Request 07CCH R DATASET1 07CDH R DATASET2 07CEH R USB_STATE 07CFH W EOP 07D0H W COMMAND 07D1H R W EPx_SINGLE1 07D2H R W EPx_SINGLE2 07D3H R W EPx_BCS1 07D4H R W EPx_BCS2 07D5H Reserved 07D6H R W INT...

Page 358: ... UDC CORE SFRs 3 3 Address Read Write SFR Symbol 07E0H R W Port_Status 07E1H R FRAME_L 07E2H R FRAME_H 07E3H R ADDRESS 07E4H Reserved 07E5H Reserved 07E6H R W USBREADY 07E7H Reserved 07E8H W Set Descriptor STALL Note is not used in the TMP92CF30 ...

Page 359: ... Write R W R W R W R W R W R W R W R W Endpoint2 0782H Reset State Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 bit Symbol EP3_DATA7 EP3_DATA6 EP3_DATA5 EP3_DATA4 EP3_DATA3 EP3_DATA2 EP3_DATA1 EP3_DATA0 Read Write R W R W R W R W R W R W R W R W Endpoint3 0783H Reset State Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undef...

Page 360: ...1 Interface 00010 Endpoint 00011 etc Others Reserved 3 16 3 4 bRequest Register This register shows the bRequest field of the device request 7 6 5 4 3 2 1 0 bit Symbol REQUEST7 REQUEST6 REQUEST5 REQUEST4 REQUEST3 REQUEST2 REQUEST1 REQUEST0 Read Write R R R R R R R R bRequest 07C1H Reset State 0 0 0 0 0 0 0 0 Standard Printer class 00000000 GET_STATUS 00000000 GET_DEVICE_ID 00000001 CLEAR_FEATURE 0...

Page 361: ...o transfer index or offset 7 6 5 4 3 2 1 0 bit Symbol INDEX_L7 INDEX_L6 INDEX_L5 INDEX_L4 INDEX_L3 INDEX_L2 INDEX_L1 INDEX_L0 Read Write R R R R R R R R wIndex_L 07C4H Reset State 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit Symbol INDEX_H7 INDEX_H6 INDEX_H5 INDEX_H4 INDEX_H3 INDEX_H2 INDEX_H1 INDEX_H0 Read Write R R R R R R R R wIndex_H 07C5H Reset State 0 0 0 0 0 0 0 0 3 16 3 7 wLength Register There are...

Page 362: ...to access EP0_FIFO 3 16 3 9 Current_Config Register This register shows the present value that is set by SET_CONFIGURATION and SET_INTERFACE 7 6 5 4 3 2 1 0 bit Symbol REMOTEWAKEUP ALTERNATE 1 ALTERNATE 0 INTERFACE 1 INTERFACE 0 CONFIG 1 CONFIG 0 Read Write R R R R R R R Current_Config 07C9H Reset State 0 0 0 0 0 0 0 CONFIG 1 0 Bit1 to bit0 00 UNCONFIGURED Set to UNCONFIGURED by the host 01 CONFIG...

Page 363: ...FACE Bit 5 SET_CONFIGRATION Bit 4 GET_CONFIGRATION Bit 3 GET_DESCRIPTOR Bit 2 SET_FEATURE Bit 1 CLEAR_FEATURE Bit 0 GET_STATUS 3 16 3 11 Request Register This register shows the device request currently being executed Any bit which is set to 1 shows a request currently being executed 7 6 5 4 3 2 1 0 bit Symbol SOFT_RESET G_PORT_STS G_DEVICE_ID VENDOR CLASS ExSTANDARD STANDARD Read Write R R R R R ...

Page 364: ...ATASET2 registers are not used in the TMP92CF30 Single packet mode DATASET1 Bit0 bit2 bit4 and bit6 DATASET2 Bit0 bit2 bit4 and bit6 These bits show whether FIFO of the corresponding endpoint has data or not In receive mode endpoint if the corresponding endpoint bit is 1 FIFO contains data to be read Access EPx_SIZE register determine the size of the data that should be read and read data of this ...

Page 365: ...ite 0 to EOP EPn_EOPB after writing data to the FIFO The maximum size that can be written to A or B packet is the same as the maximum payload size If both A and B bits are 0 continuous writing of double maximum payload size is available Note3 In dual packet transmit mode if both A and B packet are empty and EOP EPn_EOPB is written 0 the NULL data is set to FIFO In single mode the NULL data is also...

Page 366: ... 0 1 1 1 0 0 EP3_STATUS 0793H 7 6 5 4 3 2 1 0 bit Symbol TOGGLE SUSPEND STATUS 2 STATUS 1 STATUS 0 FIFO_DISABLE STAGE_ERR Read Write R R R R R R R Reset State 0 0 1 1 1 0 0 EP4_STATUS 0794H 7 6 5 4 3 2 1 0 bit Symbol TOGGLE SUSPEND STATUS 2 STATUS 1 STATUS 0 FIFO_DISABLE STAGE_ERR Read Write R R R R R R R Reset State 0 0 1 1 1 0 0 EP5_STATUS 0795H 7 6 5 4 3 2 1 0 bit Symbol TOGGLE SUSPEND STATUS 2...

Page 367: ...when ACK is not received from host In this case an interrupt is not generated The hosts re try IN token transfer 100 RX_ERR UDC sets RX_ERR to status register without transmitting ACK to host when an error such as a CRC error is detected in data of received token In this case an interrupt is not generated The hosts re try and IN token transfer In case of toggle error with normal data UDC returns A...

Page 368: ... new SETUP token is received When this bit is 1 this bit is cleared to 0 by read EP0_STATUS register This bit is not cleared even if normal control transfer or other transfer is executed after To clear read this bit When software transaction is finished and UDC writes EOP register UDC shifts to status register and waits termination of status stage In this case if software is needed to confirm that...

Page 369: ... 0 EP1_SIZE_L_A 0799H 7 6 5 4 3 2 1 0 bit Symbol PKT_ACTIVE DATASIZE6 DATASIZE5 DATASIZE4 DATASIZE3 DATASIZE2 DATASIZE1 DATASIZE0 Read Write R R R R R R R R Reset State 1 0 0 0 1 0 0 0 EP2_SIZE_L_A 079AH 7 6 5 4 3 2 1 0 bit Symbol PKT_ACTIVE DATASIZE6 DATASIZE5 DATASIZE4 DATASIZE3 DATASIZE2 DATASIZE1 DATASIZE0 Read Write R R R R R R R R Reset State 1 0 0 0 1 0 0 0 EP3_SIZE_L_A 079BH 7 6 5 4 3 2 1 ...

Page 370: ... 3 2 1 0 bit Symbol PKT_ACTIVE DATASIZE6 DATASIZE5 DATASIZE4 DATASIZE3 DATASIZE2 DATASIZE1 DATASIZE0 Read Write R R R R R R R R Reset State 0 0 0 0 1 0 0 0 EP4_SIZE_L_B 07A4H 7 6 5 4 3 2 1 0 bit Symbol PKT_ACTIVE DATASIZE6 DATASIZE5 DATASIZE4 DATASIZE3 DATASIZE2 DATASIZE1 DATASIZE0 Read Write R R R R R R R R Reset State 0 0 0 0 1 0 0 0 EP5_SIZE_L_B 07A5H 7 6 5 4 3 2 1 0 bit Symbol PKT_ACTIVE DATAS...

Page 371: ...tate 0 0 0 EP3_SIZE_H_A 07ABH 7 6 5 4 3 2 1 0 bit Symbol DATASIZE9 DATASIZE8 DATASIZE7 Read Write R R R Reset State 0 0 0 EP4_SIZE_H_A 07ACH 7 6 5 4 3 2 1 0 bit Symbol DATASIZE9 DATASIZE8 DATASIZE7 Read Write R R R Reset State 0 0 0 EP5_SIZE_H_A 07ADH 7 6 5 4 3 2 1 0 bit Symbol DATASIZE9 DATASIZE8 DATASIZE7 Read Write R R R Reset State 0 0 0 EP6_SIZE_H_A 07AEH 7 6 5 4 3 2 1 0 bit Symbol DATASIZE9 ...

Page 372: ...l DATASIZE9 DATASIZE8 DATASIZE7 Read Write R R R EP7_SIZE_H_B 07B7H Reset State 0 0 0 Note EP3 4 5 6 7_SIZE_H_B registers are not used in the TMP92CF30 DATASIZE 9 7 H register Bit2 to bit0 DATASIZE 6 0 L register Bit6 to bit0 In receiving the data number of the 1 packet received from the host is shown This is renewed when data from the host is received with no error By setting EPx_MODE register th...

Page 373: ...register On reset this bit is initialized to 0 FRAME STS 1 0 H register Bit1 and bit0 0 BEFORE 1 VALID 2 LOST These bits show the status whether a frame number that is shown in the FRAME register is correct or not At the LOST status a correct frame number is undefined If this register is VALID the number that is shown to the FRAME register is correct If this register is BEFORE during SOF auto gene...

Page 374: ...PB registers are not used in the TMP92CF30 Note2 When writing to this register a recovery time of 5clocks at 12MHz is needed After writing this register insert dummy instruction of 420 ns or longer In a control transfer type dataphase write 0 to EP0_EOPB when all transmission data is written to the FIFO or read all receiving data from the FIFO The UDC terminates its status stage on this signal Whe...

Page 375: ...dware or by control through software Each bit represents a kind of request When the relevant bit in this register is set to 0 the answer is executed automatically by hardware When the relevant bit in this register is set to 1 the answer is controlled by software If a request is received during hardware control the interrupt signal INT_SETUP INT_EP0 INT_STAS INT_STAN is set to disable If a request ...

Page 376: ...eived during software control the interrupt signal is asserted and it is controlled by software 7 6 5 4 3 2 1 0 bit Symbol Soft_Reset G_Port_Sts G_DeviceId Read Write R W R W R W Request Mode 07D9H Reset State 0 0 0 Note the TMP92CF30 doed not use this register since it does not support printer class Soft_Reset G_Port_Sts G_Config Bit 7 Reserved Bit 6 SOFT_RESET Bit 5 GET_PORT_STATUS Bit 4 GET_DEV...

Page 377: ...esets the corresponding endpoint EP0 to EP3 If this COMMAND is input the corresponding endpoint is initialized CLEAR_FEATURE request stalls endpoint When this stall is cleared execute this COMMAND This command does not affect transfer mode This command initializes the following Clear toggle sequence bit of corresponding endpoint Clear STALL of corresponding endpoint Set to FIFO_ENABLE condition Cl...

Page 378: ...B_RESET from host controller it reads content of descriptor RAM automatically and it performs relevant settings If descriptor RAM is changed during system operation it must read setting again Therefore execute this command When connected to USB host this function starts reading automatically Therefore in this case it is not necessary to execute this command 1010 FIFO_CLEAR This COMMAND initializes...

Page 379: ...Default Read Write R W R R USB STATE 07CEH Reset State 0 0 1 Note When writing to this register a recovery time of 5clocks at 12MHz is needed After writing this register insert dummy instruction of 420 ns or longer Inside the UDC the answer for each Device Request is managed by referring to these bits Configured Addressed and Default If transaction for SET_CONFIG request is executed by using softw...

Page 380: ...oftware control after INT_SETUP interrupt is received finish writing before accessing EOP register This register prohibits writing when it is other timing and it is ignored Note1 When writing to this register a recovery time of 5clocks at 12MHz is needed After writing this register insert dummy instruction of 420 ns or longer Note2 When writing to this register endpoint is initialized same as RESE...

Page 381: ...INGLE bit becomes valid in the following content 0 DUAL mode 1 SINGLE mode If setting content of EPx_SINGLE bit to valid set EPx_SELECT bit to 1 0 Invalid 1 Valid 3 16 3 26 EPx_BCS Register This register sets mode of access to FIFO in each endpoint 7 6 5 4 3 2 1 0 bit Symbol EP3_SELECT EP2_SELECT EP1_SELECT EP3_BCS EP2_BCS EP1_BCS Read Write R W R W R W R W R W R W EPx_BCS1 07D3H Reset State 0 0 0...

Page 382: ...en 0 after release of USB_RESET If the pull up resistor on D signal is controlled by control signal when pull up resistor is connected to host in OFF condition this condition is equivalent condition with USB_RESET signal by pull down resistor on the host side Therefore UDC is not detected in USB_RESET until 0 is written to USBREADY register Note1 External pull up resistor and control switch are ne...

Page 383: ...efined Undefined Undefined Undefined Undefined Read Write timing is only possible before detection of USB_RESET or during processing of SET_DESCRIPTOR request SET_DESCRIPTOR request processes from INT_SETUP assert until access of EOP register If there is rewriting request of descriptor in SET_DESCRIPTOR process the request in the following sequence 1 Read every packet of the descriptor that is tra...

Page 384: ... bytes Note 6 Possible timing in RD WR of descriptor RAM is only before detection of USB_RESET and processing of SET_DESCRIPTOR request Prohibit access other than this timing Writing must finish before connection to USB host and processing of SET_DESCRIPTOR request SET_DESCRIPTOR request processes from INT_SETUP assert until access of EOP register Note 7 The class descriptor and the vender descrip...

Page 385: ...riptor 512H 09H BLength 513H 02H bDescriptorType Config Descriptor 514H 4EH wtotalLength L 78 bytes 515H 00H wtotalLength H 516H 01H bNumInterfaces 517H 01H bConfigurationValue 518H 00H iConfiguration 519H A0H bmAttributes Bus powered remote wakeup 51AH 31H MaxPower 98 mA Interface0 Descriptor AlternateSetting0 51BH 09H bLength 51CH 04H bDescriptorType Interface Descriptor 51DH 00H bInterfaceNumbe...

Page 386: ...3DH 82H bEndpointAddress IN 53EH 02H bmAttributes BULK 53FH 40H wMaxPacketSize L 64 bytes 540H 00H wMaxPacketSize H 541H 00H bInterval Interface0 Descriptor AlternateSetting2 542H 09H bLength 543H 04H bDescriptorType Interface Descriptor 544H 00H bInterfaceNumber 545H 02H bAlternateSetting AlternateSetting2 546H 03H bNumEndpoints 547H FFH bInterfaceClass 548H 00H bInterfaceSubClass 549H FFH bInter...

Page 387: ... Descriptor1 562H 00H bLength Length of String Descriptor2 563H 00H bLength Length of String Descriptor3 String Descriptor0 564H 04H bLength 565H 03H bDescriptorType String Descriptor 566H 09H bString Language ID 0x0409 567H 04H bString String Descriptor1 568H 10H bLength 569H 03H bDescriptorType String Descriptor 56AH 00H bString Toshiba 56BH 54H bString T 56CH 00H bString 56DH 6FH bString o 56EH...

Page 388: ...ws D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 Remote wakeup Self power D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 0 0 0 Remote wakeup Reinstates current remote wakeup setting This bit is set or reset by SET_FEATURE or CLEAR_FEATURE request Default is 0 Self power Reinstates current power supply setting This bit return Self or Bus Power according to value that is set to bmAttributes field in Config descripto...

Page 389: ...HALT state following is set Initialize FIFO Clear the toggle sequence bit Clear STALL state Feature selector except 0 STALL state Note Stalls if request is to non existent endpoint 3 SET_FEATURE request This request sets or enables the relevant function bmRequestType bRequest wValue wIndex wLength Data 00000000B 00000001B 00000010B SET_ FEATURE Feature selector 0 Interface endpoint 0 None Receptio...

Page 390: ...uestType bRequest wValue wIndex wLength Data 10000000B GET_ DESCRIPTOR Descriptor type and Descriptor index 0 or Language ID Descriptor length Descriptor Device Device transmits device descriptor that is stored in descriptor RAM Config Config transmits config descriptor that is stored in descriptor RAM At this point it transmits not only config descriptor but also interface and endpoint descriptor...

Page 391: ... access EOP register and write 0 to EP0_EOPB bit so status stage is finished The process is the same for a vendor request Please refer to vendor request section 7 GET_CONFIGURATION request This request returns configuration value of present device bmRequestType bRequest wValue wIndex wLength Data 10000000B GET_ CONFIG 0 0 1 Configuration value If it is not configured it returns 0 Otherwise it retu...

Page 392: ...ified interface it enters STALL state 11 SYNCH_FRAME request This request transmits synchronous frame of endpoint bmRequestType bRequest wValue wIndex wLength Data 10000010B SYNCH_FRAME 0 Endpoint 2 Frame No Automatic answer of this request is not supported According to INT_SETUP interrupt if request received has been identified as a SYNCH_FRAME request write 2byte data in Frame No after confirmin...

Page 393: ...it confirming whether EP0_DSET_A bit in DATASET register is 0 INT_ENDPOINT0 interrupt can be used If writing all data is finished write 0 to EP0 bit of EOP register When UDC receives this the status stage finish automatically INT_STATUS interrupt is asserted when UDC finishes status stage normally If finishing status stage normally is recognized by external application manage this stage by using t...

Page 394: ...gth registers and process each request According to application access Setup_Received register after request has been identified UDC must also be informed that the INT_SETUP interrupt has been recognized After receiving data prepared in application access DATASET register and confirm EP0_DSET is 1 After confirming read data FIFO of endpoint 0 If receiving data is more than payload write data after...

Page 395: ... Check DATASET register Transmit Total_Length calculation Total payload WR number of payload to EP0_FIFO register Total Total payload Total payload WR number of rest data to EP0_FIFO Total 0 EP0 bit 1 EP0 bit 0 Receive except INT_STATUS Receive INT_STAS Status finish process in UDC Check DATASET register Receive Total_Length calculation Total payload RD number of payload from EP0_FIFO register Tot...

Page 396: ...es not accord the UDC ignores this token Endpoint field If sub channels of more than two is needed in fields of 4 bits it decides the function The UDC can support a maximum of seven endpoints excluding the control endpoint Tokens for endpoints that are not permitted are ignored Frame number field A field of 11 bits is added by the host at each frame This field follows the SOF token that is transmi...

Page 397: ...ion is of data flow up until FIFO a Bulk transfer type Bulk transfer type warrants transferring no error between host and function by using detect error and retry Basically 3 phases are used token data and handshake However with flow control and a STALL condition data phase is changed to hand shake phase and it become to 2 phases The UDC holds status of each endpoint and flow control is controlled...

Page 398: ...nd state returns to IDLE If data number of 1 packet is prepared to FIFO it shifts to 3 3 Data packet is generated Data packet generated by using toggle bit register in UDC Next data is transferred from FIFO of internal UDC to SIE and data packet is generated At this point the confirms transferred data number is confirmed And if there is more than the maximum payload size of each endpoint bit stuff...

Page 399: ...D Attach DATA0 DATA1 Confirm Datasize register Transmit data OK OK OK Attach CRC OK Receive ACK Wait for ACK from host Normal finish transaction Clear FIFO Clear DATASET register Renew toggle bit Set STATUS to READY OK Time out Set STATUS to TX_ERR Put back FIFO addless pointer Bit stuff error Set STATUS at STALL ConfirmToken packet PID Address Endpoint Transfer mode Error Transmit NAK Transmit ST...

Page 400: ... SIE of internal UDC to FIFO At this point it confirms transferred data number and if there is more than the maximum payload size of each endpoint STATUS becomes to STALL and the state returns to IDLE ACK handshake does not return 4 After last data is transferred the counted CRC is compared with the transferred CRC If they do not correspond STATUS is set to RX_ERR and the state returns to IDLE At ...

Page 401: ...ATA PID DATA0 DATA1 Time out Toggle check Receive data Error Confirm receiving data number Error transaction Set STATUS at RX_ERR Put back FIFO address pointer Cancel data Cancel data Error transaction Set status at RX_ERR Data communication of more than payload Retry transaction OK Normal finish transaction Set transfer data number to DATASIZE register Set DATASET register Renew toggle bit Set ST...

Page 402: ... UDC operation is same as in bulk transmission mode Please refer to section a b 2 Interrupt transmission mode Not toggle mode This is basically the same as bulk transmission mode However if ACK handshake from host is not received transaction is different When ACK handshake from host is received after transmission of data packet Clear FIFO Clear DATASET register Renew toggle bit and prepare for nex...

Page 403: ...up stage Setup stage is the same as transmission bulk transaction except that token ID becomes SETUP However control flow in the UDC is different Token SETUP Data DATA 0 Handshake ACK Control flow Below is the control flow in the UDC when SETUP token is received 1 SETUP token packet is received and address endpoint number and error are confirmed It also checks whether the relevant endpoint is in c...

Page 404: ...iving device request is judged whether software control or hardware control If the request needs control in software INT_SETUP interrupt is asserted If hardware is used INT_SETUP interrupt is not asserted According to stage control flow prepare for next stage Set STATUS to DATAIN Set toggle bit to 1 The Setup stage is completed by the above This flow is shown in Figure 3 16 2 8 byte data that is t...

Page 405: ...nish transaction Set DATASET register Assert INT_SETUP and request flag According to stage flow prepare for next stage Set STATUS to DATAIN Set toggle bit to 1 OK Confirm Token packet PID Address Endpoint Transfer mode Error Invalid Except DATA0 PID Time out Error Error transaction Set STATUS to RX_ERR Put back FIFO address point Receive data Error Confirm receving data number Error more than payl...

Page 406: ...stage base of control flow in control transfer type At this point CPU must write 0 to EP0 bit of EOP register in last transaction for status stage to finish normally Details of status stage are given below c 3 1 IN status stage IN status stage transaction format is given below Token IN Data DATA1 0 data length NAK STALL Handshake ACK Control flow The transaction flow of IN status stage in UDC is g...

Page 407: ... If status stage is enabled base on stage control flow in the UDC advance to next stage 2 STATUS register state is confirmed INVALID condition State returns to IDLE STALL condition Data is cleared stall handshake is returned and state returns to IDLE Whether EOP register is accessed or not is confirmed externally If it is not accessed NAK handshake is returned to continue control transfer and stat...

Page 408: ...t Data stage direction Based on these it is determines to be either control read transfer type control write transfer type or control write transfer type No data stage Various conditions for changing stage in control transfer are given below If receiving token for next stage from host before switching to next stage from state of internal UDC NAK handshake is returned and BUSY is informed to USB ho...

Page 409: ...PU set short packet transfer in EOP register EP0 bit of DATASET register is set The UDC transfers data that is set to FIFO to host by IN token interrupts When the CPU finishes transaction it writes 0 to EP0 bit of EOP register Change status stage in the UDC 3 Receive OUT token from host Return ACK to OUT token and change state to IDLE in the UDC Assert INT_STATUS interrupt externally These changin...

Page 410: ...f 0 data to IN token and change state to IDLE in the UDC Assert INT_STATUS interrupt externally when ACK for 0 data packet is received These changing conditions are shown in Figure 3 16 7 Figure 3 16 7 The Control Flow in UDC Control Write Transfer Type In control read transfer type transaction number of data stage does not always correspond with the data number specified by the device request The...

Page 411: ...n recognized The CPU processes receiving data by device request When the CPU finishes transaction it writes 0 to EP0 bit of EOP register Change status stage in the UDC Return data packet of 0 data to IN token and change state to IDLE in the UDC Assert INT_STATUS interrupt externally when ACK for 0 data packet is received These change condition is Figure 3 16 8 Figure 3 16 8 The Control Flow in UDC...

Page 412: ...in the next frame Below are two conditions in FIFO of Isochronous transmission mode transferring X FIFO for storing data that transmits to host in present frame DATASET register bit 1 Y FIFO for storing data for transmitting host in next frame DATASET register bit 0 FIFO that is divided into two packet A and packet B conditions is whether X condition or Y condition The flow below is explained as X...

Page 413: ...erchanges with packet B s FIFO and transaction uses same flow If SOF token is not received by error and so on this data is lost because frame is not renewed There is no problem in receiving PID if frame data is received with CRC error USB sets LOST to STATUS on FRAME register and exact frame number is unknown However in this case SOF is asserted and FIFO condition is renewed If SOF token is receiv...

Page 414: ... Clear X condition A Set FULL to STATUS Frame number unknown Set LOST to FRAME register ReceiveSOF BANK B transaction Clear transmitting FIFO BANK A in preceding frame Clear DATASET register s BANK A bit Set DATASET register s BANK B bit Finish a write in previous frame Set STATUS to READY Wait data for transmitting next frame BANK A BANK A transaction Clear transmitting FIFO BANK B in preceding f...

Page 415: ...irmed and it checks whether the relevant endpoint transfer mode corresponds with the OUT token If it does not correspond the state returns to IDLE 2 Condition of status register is confirmed INVALID condition State return to IDLE 3 Data packet is received Data is transferred from SIE into the UDC to packet A s FIFO X Condition 4 After last data has been transferred and counted CRC is compared with...

Page 416: ...n FRAME register and exact frame number is unknown However in this case SOF is asserted and FIFO condition is renewed If SOF token is received without transmit and transfer Isochronous in frame UDC clears FIFO X Condition and sets STATUS to FULL These are shown in Figure 3 16 12 Note EPx_DATASET changes at 2 clocks of 12MHz after receiving SOF Read data from FIFO after EPx_DATASET is rising Figure...

Page 417: ...or transaction Set STATUS to RX_ERR Receive SOF BANK B transaction Set data size received preceding frame to DATASIZE register in BANK A Set BANK A bit in DATASET register Clear BANK B bit in DATASET register Set STATUS to DATAIN But if error generates set RX_ERR Shift FIFO BANK every receive SOF Error time out exept data PID Error receiving data more than payload BANK A transaction Set data size ...

Page 418: ...o used as an independent FIFO Even if the UDC is transmitting and receiving to USB host it can be used as an efficient bus by possible load to FIFO But control transfer type receives only single packet mode Epx_SINGLE signal in dual packet mode must be fixed to 0 If this signal is fixed to 0 FIFO register runs in single mode Sample Where endpoint 1 is used to dual packet of payload 64 bytes EP1_FI...

Page 419: ...e changed between single packet and dual packet by setting Epx_SINGLE register Do not change packet when transferring Figure 3 16 13 Receiving Sequence in Single Packet Mode IDLE DATASET register Check bit of EPx_DSET_A SIZE register Size of SIZE_A_L confirmation Size of SIZE_A_H confirmation RD receiving data of size in relevant endpoint DATASET 1 DATASET register Set bit of EPx_D SET_A Assert EP...

Page 420: ...ster Check bit of EPx_DSET_A Distinction transmitting number EOP register Write 0 to only bit of relevant endpoint If transmitting number reach to payload UDC sets 1 to relevant bit of DATASET register UDC sets 1 to relevant bit of DATASET register Return to IDLE When receiving In Token from USB Host UDC transmits data Clear relevant bit of DATASET register Accessing to EOP register is needed in t...

Page 421: ..._ACTIVE bit If PKT_ACTIVE bit has been set to 1 that packet is received first Packet A and packet B set data turn about always This is shown below Figure 3 16 15 Receiving Sequence in Dual Packet Mode IDLE DATASET register Check bit of EPx_DSET_A Check bit of EPx_DSET_B SIZE register Confirm Size of SIZE_A_L Confirm Size of SIZE_A_H Confirm Size of SIZE_B_L Confirm Size of SIZE_B_H Read size of re...

Page 422: ...f transmitting in relevant endpoint Total 0 EOP register Write 0 to only bit of relevant endpoint If transmitting number reach to payload UDC sets 1 to relevant bit of DATASET register Accessing to EOP register is needed in transmitting short packet Control transfer type is supported in only single mode Transmitting number payload number of available packet Write number of payload number of availa...

Page 423: ...NULL packet in a certain period it is answered by keeping EPx_EOPB signal to L level However if mode is dual packet mode EPx_DATASET signal assert L level for showing space of data Therefore data condition whether either has data or not cannot be confirmed externally Note NULL packet can also be set by accessing EOP register Example 2 Interrupt control Interrupt signal is prepared This function us...

Page 424: ... is prohibited Register name Initial value ENDPOINT STATUS EP0 00H Except for EP0 1CH 2 Detail of STATUS register Status register that has been prepared for each endpoint shows the condition of each endpoint in the UDC Each condition affects the various USB transfers Refer to chapter 5 for the changing conditions for each transfer type EPx_STATUS register value is 0 to 3 and its shows conditions a...

Page 425: ...ives ID of status stage from USB host BUSY is set STATUS is BUSY until CPU finishes enumeration transaction and EP0 bit of EOP register is written 0 in UDC If CPU enumeration transaction finishes and EP0 bit of EOP register is written 0 and status stage from USB host finishes normally it displays READY 6 STALL STALL shows that endpoint is in STALL condition This condition is generated if it violat...

Page 426: ...NTMR2 and USBCR1 2 Return from suspend condition by host resume When activity of bus on USB signal is restored by resume condition output from USB host the UDC releases SUSPEND condition and it resets SUSPEND bit of STATUS register to 0 The system is thereby resumed The resume condition output from the host is maintained for at least 20 ms Therefore effective protocol occurs on USB signal line aft...

Page 427: ...UDC can be controlled by using USBINTFR1 INT_SUS INT_CLKSTOP and USBCR1 USBCLKE If UDC switches to suspend condition USBINTFR1 INT_SUS is set to 1 and INT_CLKSTOP is set to 1 After confirmation stop CLK supply USBCLK by setting 0 to USBCR1 USBCLKE If SUSPEND condition is released by resuming from host supply normal CLK to UDC within 3 ms When remote wakeup is used it is necessary to supply a stabl...

Page 428: ... When UDC stops CLK in suspend condition UDC can not detect USB reset and control CLK in suspend condition as above mentioned In case CLK is stopped in suspend condition UDC can detect USB reset and return from suspend condition by supplying CLK USBCR1 USBCLKE 1 after detecting INT_CLKON interrupt ...

Page 429: ...T_ ENDPOINT0 INT_STATUS REQUEST FLAG EP0 FIFO access Request access Setup Received access IN ACK IN ACK OUT ACK EOP register access Stage error SETUP DATA0 ACK IN NAK DATA1 DATA0 DATA0 INT_SETUP INT_ ENDPOINT0 INT_STATUS REQUEST FLAG EP0 FIFO access Request access Setup Received access IN ACK IN ACK ACK EOP register access SETUP Stage error bit STATUS register read Normal Normal ...

Page 430: ...ent_Config 0x00 0x00 EPx_SIZE_H_B 0x00 0x00 Standard request 0x00 0x00 FRAME_L 0x00 0x00 Request 0x00 0x00 FRAME_H 0x02 0x02 DATASET 0x00 0x00 ADRESS 0x00 0x00 Port Status 0x18 Hold EPx_SINGLE 0x00 Hold Standard request mode 0x00 Hold EPx_BCS 0x00 Hold Request mode 0x00 Hold ID_STATE 0x01 0x00 Note 1 The above initial value is the value that is initialized by external reset USB_RESET This value ma...

Page 431: ...control flow chart a Transaction for standard request Outline flowchart Example USB interrupt Call USBINT0 function Evaluate Interrupt SETUP transaction ENDPOINT 0 transaction STATUS transaction STATUS NAK transaction ENDPOINT 1 transaction ...

Page 432: ...ition change Initialization transaction Turn on power supply Waiting USB interrupt condition Request transaction condition Receive USB token Transmit Request error Transmit STALL Transaction error Transmit STALL Normal finish No transaction ...

Page 433: ...rt Get request data Evaluate Request End Standard request CLEAR_FEATURE SET_FEATURE GET_STATUS SET_ADDRESS SET_CONFIGURATION GET_CONFIGURATION SET_INTERFACE GET_INTERFACE SYNCH_FRAME GET_DESCRIPTOR Class request Error for not support Vendor request Error for not support Error transaction ...

Page 434: ...09 06 12 92CF30 432 c 1 CLEAR_FEATURE request transaction Start End Is request right Finish transaction Error transaction No Yes Evaluate Recipient Device Disable remote wakeup setting Endpoint Clear stall setting ...

Page 435: ...CF30 2009 06 12 92CF30 433 c 2 SET_FEATURE request transaction Start End Is request right Finish transaction Error transaction No Yes Evaluate Recipient Device Enable remote wakeup setting Endpoint Set stall ...

Page 436: ...c 3 GET_STATUS request transaction Start End Is request right Finish transaction Error transaction No Yes Evaluate Recipient Interface Set 0 x 0 0 data of 2 bytes Endpoint Set stall information Device Set self power supply information ...

Page 437: ... 4 SET_CONFIGRATION request transaction Start End Is request right Finish transaction Error transaction No Yes Is EP0 stall Is assignment value valid Is state valid Set assigned configuration value Clear stall flag No No No Yes Yes Yes ...

Page 438: ...TMP92CF30 2009 06 12 92CF30 436 c 5 GET_CONFIGRATION request transaction Set present configuraion value Start End Is request right Finish transaction Error transaction No Is state valid No Yes Yes ...

Page 439: ... c 6 SET_INTERFACE request transaction Start End Is request right Finish transaction Error transaction No Yes Is EP0 stall Is assigned value valid Is state valid Set each endpoint to assigned configuration value No No No Yes Yes Yes ...

Page 440: ... 7 SYNCH_FRAME request transaction Start End Is request right Finish transaction Error transaction No Yes Is EP0 stall Is assigned value valid Is state valid Set alternate setting value to present transmitting data No No No Yes Yes Yes ...

Page 441: ...CF30 439 c 8 SYNCH_FRAME request transaction c 9 SET_DESCRIPTOR request transaction Start End Is request right Finish transaction Error transaction No Yes Start End Is request right Finish transaction Error transaction No Yes ...

Page 442: ...nd Is request right Write information to FIFO EP0_fifowrite Error transaction No Yes Is EP0 stall Is assigneed value valid Is state valid No No No Yes Yes Yes String Set string descriptor information Config Set config descriptor information Device Set device descriptor information ...

Page 443: ...o FIFO by EP0 Start End Is request right No Yes Stage information data stage STATUS_NAK interrupt enable Data read from FIFO All data number renew transfer address Read data from FIFO STATUS_NAK interrupt disable Stage information status stage Finish transaction ...

Page 444: ...ion data stage STATUS_NAK interrupt enable Set data size to SIZE register All data number renew former transfer address Write data to FIFO STATUS_ NAK interrupt disable Stage information status stage Finish transaction Write data to FIFO Set transmitting size to SIZE register Yes No Is data number a multiple of payload size ...

Page 445: ...f microcontroller c 14 Initial setting transaction of UDC Start End USBC reset transaction Start Set Stack point Clear vRAM USB firmware initialization USB_INIT Interrupt disable Set Various interrupts UDC initialization UDC_INIT Interrupt enable Main transaction main ...

Page 446: ...f USB number changing firmware c 16 Set DEVICE_ID data to DEVICE_ID of UDC Start End Renew stage information Renew current information Renew support information Invalid EP except EP0 Various flag Intialization Start End Set DEVICE_ID data to DEVICE_ID_RAM area ...

Page 447: ...t End Set descriptor data to DESC_RAM area Start Evaluate Interrupt Read INT register End Evaluate Request transaction STATUS_judge Setup interrupt transaction Proc_SETUPINT Endpoint 0 interrupt Proc_ ENDPOINT Status_NAK interrupt Proc_STATUSNAKINT Status_interrupt Proc_STATUSINT Others Error transaction ...

Page 448: ...rms nothing therefore outline flow is skipped c 20 Request evaluation transaction If transaction result is error it initiates STALL command c 21 SETUP stage transaction Start End Is request right No Yes Error transaction Start End Is request right No Yes Stage information SETUP stage Request transaction ...

Page 449: ...SETUP stage c 23 Status stage interrupt transaction Start End Evaluate Stage Others Error transaction Status stage Finish normally Data stage GET system request EP0_fifowrite SET system request EP0_fiforead Start End Status stage Error transaction Normal finish transaction No Yes ...

Page 450: ...2CF30 2009 06 12 92CF30 448 c 24 STATUS_NAK interrupt transaction c 25 This transaction is a non transaction for USB interrupts Start Start End Data stage Error transaction Normal finish transaction No Yes ...

Page 451: ...ated to standard request Start End Is config within support No Yes Get device information on descriptor Interface is within support in config present No Yes Get config information on descriptor Get device information on descriptor Increment count to next config information ...

Page 452: ... packets to determine which packet should be processed first At this time the following precaution is required The EPx_SIZE register that indicates the presence of valid data is provided separately for packets A and B The CPU is required to check the respective PKT_ACTIVE bits to determine which packet was accessed first and then to know the number of data in this packet The packet with its PKT_AC...

Page 453: ...d Rate 20 Mbps max 4 Can be connected to multiple SD cards and the MMC Since there is only on chip select signal preassigned as SPCS use other output ports to allow for more than two connections This device has 1 channel SPI circuit It shared with PR0 PR3 pins However it is possible also that it assign SPI function to PC4 PC6 pins 5 Operates as the general synchronous SIO Selects the followings MS...

Page 454: ...d under real world conditions Note 2 Any one of general inputs and interrupt should be used as the WP Write Protect and CD Card Detect inputs respectively Figure 3 17 1 Block Diagram and Connection Example fSYS Baud Rate Generator SPIMD CT 16 bits SPCLK SPCS SPIIE 16 bits SPICR SPIC SPI Controller SD Card SCLK CS Port WP Write Protect INTn CD Card Detect 100kΩ 100kΩ SPIST 16 bits INTSPI 16 bits SP...

Page 455: ...ion Reception 0 LSB 1 MSB SPDO Pin State When Not Transmitting 0 Fixed to 0 1 Fixed to 1 Synchronizati on Clock Edge Select for Transmission 0 Falling edge 1 Rising edge Synchronizat ion Clock Edge Select for Reception 0 fall 1 rise Data Inversion for Transmissio n0 Disable 1 Enable Data Inversion for Reception 0 Disable 1 Enable Note The SD card of the TMP92CF30 supports a baud rate of up to 20 M...

Page 456: ...7 4 Timing Diagram of Data Transmissions Controlled by the TCPOL Bit e RCPOL This bit specifies the polarity of the active edge of the synchronization clock for data reception The SPIMD XEN bit should be cleared to 0 for changing the state of this bit TCPOL should also be cleared to 0 Figure 3 17 5 Timing Diagram of Data Receptions Controlled by the TCPOL Bit f TDINV This bit specifies whether to ...

Page 457: ...ing there is no UNIT data currently being received or the receive operation can be stopped completely by writing a 1 to the SWRST bit after checking no UNIT data in receiving namely after REND interrupt or the time to receive 1UNIT Do not write a 1 to the SWRST bit during a data reception Software reset can be performed in a single shot operation which is to write a 1 to the SWRST bit it is not re...

Page 458: ...e 0 Disable 1 Enable Receive Mode Select 0 UNIT 1 Sequential Receive Enable 0 Disable 1 Enable 15 14 13 12 11 10 9 8 Bit Symbol CRC16_7_B CRCRX_TX_B CRCRESET_B Read Write R W Reset State 0 0 0 0823H Function CRC Select 0 CRC7 1 CRC16 CRC Data 0 Transmit 1 Receive CRC Calculation Register Control 0 Reset 1 Reset Release Figure 3 17 6 SPICT Register a CRC16_7_B This bit selects the CRC calculation a...

Page 459: ...lculation is performed 2 To reset the SPICR register write a 0 to the CRCRESET_B bit and then write a 1 to the same bit 3 Load the SPITD register with the transmit data and wait until transmission of all data is completed 4 Read the SPICR register and obtain the result of the CRC calculation 5 Transmit the CRC obtained in step 4 in the same way as step 3 The CRC calculation on the receive data can...

Page 460: ...uld be set to 1 when performing the full duplex communication This bit specifies whether to align the transmit and receive data on the UNIT size boundaries Data transmission or reception must not be performed while changing the state of this bit h TXMOD This bit selects the data transmission mode from UNIT and Sequential modes During transmission it is prohibited to change the transmission mode fr...

Page 461: ...ion end flag SPIST TEND 1 LD SPITDx A Load A the transmit data DI Disable the interrupt SET 3 SPICT Start transmission be setting the TXE bit to 1 RES 3 SPICT Disable the transmission by clearing the TXE bit to 0 EI Enable the interrupt j RXMOD This bit selects the data reception mode from UNIT and Sequential modes During reception it is prohibited to change the reception mode from Sequential to U...

Page 462: ...Controller supports six operating modes as listed below These are specified by the FDPXE RXMOD RXE TXMOD TXE bits Table 3 17 2 Data Transmission Reception Modes Bit Settings Operating Mode FDPXE TXMOD TXE RXMOD RXE Description 1 UNIT transmission 0 0 1 x x Transmit the SPITD data per UNIT 2 Sequential transmission 0 1 1 x x Transmit the FIFO data sequentially 3 UNIT reception 0 x x 0 1 Receive onl...

Page 463: ...ait BIT 1 SPIST Wait for the completion of the transmission JPZ Wait RES 3 SPICT Disable the transmission by clearing the TXE bit to 0 EI Enable the interrupt Sample Program 2 Recommend Check the transmission end flag SPIST TEND 1 LD SPITDx A Load A the transmit data DI Disable the interrupt SET 3 SPICT Start transmission be setting the TXE bit to 1 RES 3 SPICT Disable the transmission by clearing...

Page 464: ...o the SPICT TXE bit during a transmission stops the transmission after completing the transmission of the UNIT data currently being transmitted The TEMP interrupt is generated when the empty space size of the FIFO becomes 16 or 32 bytes The TEND interrupt is generated upon completion of the transmission of the last UNIT data ...

Page 465: ...shift register The Sequential mode reception automatically receives the data as long as the receive FIFO has any empty space The Sequential mode is selected by writing a 1 to the SPICT RXMOD bit The 32 byte receive FIFO is disabled in this mode In this reception mode the data reads from the receive FIFO must be performed in 16 byteunits Otherwise the RFUL interrupt is not properly generated Receiv...

Page 466: ...me time has not been prepared Transmit and receive operation is started only after the transmit data is written into the SPITD register where SPICT TXE 1 The figure below shows the operations of the receiver and transmitter for the simultaneous transmit and receive operation Note If the data transmission and reception are not performed simultaneously data communication should be performed with the...

Page 467: ...e TEMP interrupt is generated by the following two conditions One is when the empty space size of the transmit FIFO reaches 16 bytes and the other is when it reaches 32 bytes The TEND interrupt is generated when the transmission of the last UNIT data is completed with the FIFO being empty i e after the falling edge of the last bit clock where SPIMD TCPOL 0 b Receive interrupts RFUL Receive FIFO in...

Page 468: ...n this bit is set to 1 when the transmit FIFO buffer contains no valid data b TEND This bit is cleared to 0 when the SPITD register or the transmit FIFO contains valid transmit data and also when the transmission is in progress This bit is set to 1 after completing the data transmission where the SPITD register and the transmit FIFO contain no valid data c REND For UNIT mode reception this bit is ...

Page 469: ...es or disables the TEMP interrupt b RFULIE This bit enables or disables the RFUL interrupt c TENDIE This bit enables or disables the TEND interrupt d RENDIE This bit enables disables the REND interrupt Note The SPIC supports four types of interrupts two transmit interrupts TEMP and TEND both of which causes the generation of the INTSPITX interrupt request and two receive interrupts RFUL and REND b...

Page 470: ...C generation The following describes the steps required to calculate the CRC16 for the transmit data First initialize the CRC calculation register by writing a 1 to the CRCRESET_B bit after programming three bits as follows CRC16_7_b 1 CRCRX_TX_B 0 and CRCRESET_B 0 Then by writing the transmit data into the SPITD register complete the transmission of all bits for which the CRC should be calculated...

Page 471: ...g the transmit data When this register is read the last written data is read out This register is overwritten if the next data is written with the transmit FIFO being full Since the transmit data registers can contain data of up to four bytes it can support write operations that are performed by using four byte instructions such as the parallel operation of the SPI and DMA When writing the data th...

Page 472: ... up to four bytes it can support read operations that are performed by using four byte instructions such as the parallel operation of the SPI and DMA When reading the data the receive data at the address 834 should be the first to be read There are some exceptions There are several restrictions of the data reading methods i e instructions to be used For mode details please refer to the following t...

Page 473: ... software In the Sequential mode reception the data reads from the receive FIFO must be performed in 16 byte units Otherwise the RFUL interrupt is not properly generated Note For data reception in units of other than 16 bytes UNIT mode must be selected 3 CRC The CRC is generated upon transmission and reception to from the SPI slave device Refer to the section on the SPICRC register fro more detail...

Page 474: ...tures Item Description Number of Channels 1 channel Format I 2 S format compliant Right justified and left justified formats supported Stereo monaural Master transmission only Pins used 1 I2S0CKO clock output 2 I2S0DO output 3 I2S0WS Word Select output WS frequency Data transfer rate Refer to Setting the transfer clock generator and Word Select signal Transmission buffer 64 bytes 2 Direction of da...

Page 475: ...1 31 Data Selector Interrupt Control Read Pointer FIFO Control I2SBUF0 INTI2S0 32bit I2S0CTL DTFMT01 00 DIR0 BIT0 WLVL0 Internal Data Bus Write Pointer Counter Stop I2S0CTL CNTE0 I2S0C WS05 00 6 bit Counter Clock Generator 64 byte FIFO1 2 bytes 32 0 1 31 fPLL Request Signal Output to ADC Supported in channel 0 only I2S0CTL CLKS0 I2S0C CK07 00 8 bit Counter I2SCKO Invert I2S0CTL EDGE0 I2S0DO ...

Page 476: ...WS level 0 Low left 1 High left Data output clock edge 0 Falling 1 Rising Clock operation after transmis sion 0 Enable 1 Disable I2 S0 Divider Value Setting Register 7 6 5 4 3 2 1 0 bit Symbol CK07 CK06 CK05 CK04 CK03 CK02 CK01 CK00 Read Write R W Reset State 0 0 0 0 0 0 0 0 Function Divider value for CK signal 8 bit counter I2S0C 180AH 15 14 13 12 11 10 9 8 Bit symbol WS05 WS04 WS03 WS02 WS01 WS0...

Page 477: ...sible to change data direction during data transmission Before changing the data format set SYSCKE0 1 CNTE0 0 and TXE0 0 e CNTE0 This bit controls clock generator counter Clear Start When this circuit is used always set to the start condition Clock generator counter will clear by TXE0 0 and CNTE0 0 However Clock generator counter will not clear by TXE0 0 and CNTE0 1 f TXE0 This bit controls data t...

Page 478: ...FIFO buffer is empty TEMP0 0 remain data in FIFO buffer This bit is read only FIFO buffer is cleared by TXE0 0 k FSEL0 This bit controls sound mode Stereo Monaural FSEL0 0 Stereo FSEL0 1 Monaural Refer the chapter of Data format in details It is not possible to change sound mode during data transmission Before changing the data format set SYSCKE0 1 CNTE0 0 and TXE0 0 l CLKS0 This bit controls sour...

Page 479: ...nerates the I2S0WS signal by dividing the I2S0CKO signal B Word Select Word Select signal I2S0WS The I2S0WS signal is used to distinguish the position of valid data and whether left data or right data is being transmitted in the I2S format This signal is clocked out in synchronization with the data transfer clock In only channel 0 this signal can be used as an AD conversion trigger signal for the ...

Page 480: ... the same data written to the FIFO buffer The Monaural function of TMP92CZ26A CF26A and TMP92CF30 is different The Monaural function of TMP92CZ26A CF26A is one of channels only Figure3 18 3 Output Format LSB MSB LSB MSB LSB MSB I2S0WS LSB MSB LSB MSB LSB Valid data Valid Data Valid Data Valid Data MSB LSB MSB LSB MSB Left justify I2S0DO Stereo Valid Data Valid Data Right Data Left Data Right justi...

Page 481: ... CLKS0 An 8 bit counter is provided to divide the source clock by 3 to 256 The divider value cannot be set to 1 or 2 The transfer clock must not exceed 10 MHz Make sure that the transfer clock is set to within 10 MHz by an appropriate combination of source clock frequency and divider value 8 bit counter set value Divider value 00000000 256 00000001 1 11111111 255 When fSYS 60 MHz and I2S0C CK07 00...

Page 482: ...for I 2 S transfer when the data length is 8 bits and 32 or larger 34 or larger for I 2 S transfer when the data length is 16 bits Note 2 It is recommended that the value to be set in I2S0C WS05 00 be an even number Although it is possible to set an odd number the clock duty of the WS signal does not become 50 Setting an odd number causes the High width of the WS signal to become longer by one I2S...

Page 483: ...wed and transmission isn t started And window addresses are 1800H channel 0 and 1810H channel1 Write Data Size Example instruction 8 bit width 16 bit width 1 byte access ld 0x1800 a Not allowed Not allowed 2 byte access ld 0x1800 wa Not allowed Not allowed 4 byte access ld 0x1800 xwa OK OK Also note that data must be written in units of 64 bytes using the following sequence 4 byte load instruction...

Page 484: ...6 5 4 3 2 1 0 MSB first 16 bits LSB first 16 bits Output order MSB first 8 bits LSB first 8 bits MSB first 16 bits LSB first 16 bits MSB first 8 bits LSB first 8 bits 2 nd Data 1 st Data 4 th Data 3 rd Data 2 nd Data 1 st Data 1 st Data 2 nd Data 1 st Data 2 nd Data 3 rd Data 4 th Data I2S0BUF register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSB first ...

Page 485: ... be written to the FIFO in the interrupt routine Example settings and timing diagram are shown below Example settings I2S0WS 8kHz I2S0CKO 400kHz data transmission on the rising edge at fSYS 60 MHz Main routine 7 6 5 4 3 2 1 0 INTEI2S01 X X 0 0 1 Set interrupt level PFCR X X PFFC X 1 1 1 Set pins PF0 I2S0CKO PF1 I2S0DO PF2 I2S0WS 1 0 0 1 0 1 1 0 Divider value N 150 I2S0C X X 1 1 0 0 1 0 Divider val...

Page 486: ...s I 2 S FMT Stereo 16bit MSB first FIFO write TXE I2S0WS pin I2S0CKO pin I2S0DO pin INTI2S0 1 3 31 33 Overall Timing Diagram LSB MSB LSB MSB LSB MSB I2S0WS pin I2S0CKO pin I2S0DO pin Detailed Timing Diagram 400kHz Bit15 Bit14 Bit0 Bit15 Bit14 Bit0 Bit15 2 4 32 ...

Page 487: ...he I2S0CTL TEMP0 flag Then after waiting for two periods of the I2S0WS signal after all the data has been transmitted set TXE0 to 0 In case monaural setting make sure that the FIFO is empty by checking the I2S0CTL TEMP0 flag Then after waiting for four periods of the I2SWS signal after all the data has been transmitted set TXE0 to 0 If TXE0 is set to 0 while data is being transmitted the transmiss...

Page 488: ...ed In case monaural setting make sure that the FIFO is empty by checking the I2S0CTL TEMP0 flag Then after waiting for four periods of the I2S0WS signal after all the data has been transmitted set TXE0 to 0 5 I2S0BUF When writing data to the I2S0BUF register be sure to use long word data load instructions Word data load or byte data load instructions cannot be used Examples ld I2S0BUF xwa OK ld I2...

Page 489: ...TSICR0 and TSICR1 and using an internal AD converter 3 19 1 Touch Screen Interface Module Internal External Connection Figure 3 19 1External connection of TSI Figure 3 19 2 Internal block diagram of TSI External Capacitors MY MX PY PX TMP92CF30 Y Y Touch Screen X X AVSS P96 INT4 PX P97 PY VREFH VREFL PXEN PYEN MXEN MYEN AN3 AN2 PG3 AN3 MY AVCC PG2 AN2 MX VREFH VREFL AVCC AVSS AD converter Touch sc...

Page 490: ...the CPU clock is used for the debounce circuit the debounce circuit does not operate and also no interrupts that bypass the debounce circuit are generated during IDLE1and STOP mode During IDLE1 or STOP mode set this circuit to disable Write 0 in TSICR1 DBC7 before entering the HALT state If debounce time is set to 0 the signal is captured into the inside after a count of 6 system clocks fSYS from ...

Page 491: ...n is set to Low by the internal pull down resistor PXD generating no INT4 interrupt When a next pen touch is given the X and Y direction internal resistors in the touch screen are connected which sets the P96 INT4 PX pin to High and generates an INT4 interrupt To avoid generating more than one INT4 interrupt by one pen touch the debounce circuit as shown below is provided Setting debounce time in ...

Page 492: ...nce time counter Debounce time Debounce time The debounce time counter matches with a specified debounce time which generates an INT4 interrupt After the pen is released an INT4 interrupt can be received again Debounce time No INT4 interrupt is generated due to edge interrupt even though the debounce time counter matches a specified debounce time ...

Page 493: ...ition measurement above can be determined with the ratio between the ON resistance value of the switch in the TMP92CF30 and the resistance value in the touch screen as shown in Figure 3 19 5 Therefore even when touching an end area on the touch screen the analog input voltage will be neither 3 3V nor 0 0V Note that the rate of each resistance varies Remember to take this into consideration during ...

Page 494: ...H TSICR1 XXH voluntary 1 Touch Detection Procedure INT4 Routine 2 X Y Position Measuring Procedure Yes No Return to the Main Routine Main Routine X position measurement TSICR0 C5H AN3 AD conversion Store the AD conversion result Y position measurement TSICR0 CAH AN2 AD conversion Store the AD conversion result Execute the processes by using X Y coordinate position information Still touched TSICR0 ...

Page 495: ...interrupt level of INT4 tsicr0 98h Pull down resistor on SPY on Interrupt set TWIEN ei Enable interrupt X AVSS PX P96 INT4 PY P97 VREFH VREFL PXEN PYEN MXEN MYEN AN3 AN2 MY PG3 AVCC MX PG2 VREFH VREFL AVCC AVSS AD Converter Touch screen control TSI7 SPY SPX SMX SMY PXD typ 50kΩ Dec INT4 PTST Internal data bus Y Y Touch Screen X TMP92CF30 ON ON ...

Page 496: ...Set the input gate of P97 P96 to OFF admod1 b0h Set to AN3 admod0 08h Start AD conversion AVSS PX P96 INT4 PY P97 VREFH VREFL PXEN PYEN MXEN MYEN AN3 AN2 MY PG3 AVCC MX PG2 VREFH VREFL AVCC AVSS AD Converter Touch screen control TSI7 SPY SPX SMX SMY PXD typ 50kΩ Dec INT4 PTST Internal data bus Y Y Touch Screen X X TMP92CF30 ON ON ...

Page 497: ...Set the input gate of P97 P96 to OFF admod1 a0h Set to AN2 admod0 08h Start AD conversion AVSS PX P96 INT4 PY P97 VREFH VREFL PXEN PYEN MXEN MYEN AN3 AN2 MY PG3 AVCC MX PG2 VREFH VREFL AVCC AVSS AD Converter Touch screen control TSI7 SPY SPX SMX SMY PXD typ 50kΩ Dec INT4 PTST Internal data bus Y Y Touch Screen X X TMP92CF30 ON ON ...

Page 498: ...g from the state during IDLE1 and STOP modes set the debounce circuit to disable before entering the HALT state TSICR1 DBC7 0 2 Port setting When an intermediate voltage of 0 V to AVcc is converted using the AD converter the intermediate voltage is also applied to the normal C MOS input gates P96 and P97 due to the circuit structure Take measures against the flow through current to Port 96 and 97 ...

Page 499: ...he year following 99 is 00 years In use please take into account the first two digits when handling years in the western calendar Note 2 Leap year A leap year is divisible by 4 but the exception is any leap year which is divisible by 100 this is not considered a leap year However any year which is divisible by 400 is a leap year This product does not take into account the above exceptions Since th...

Page 500: ...W R W RESTR 1328H 1Hz enable 16Hz enable Clock reset Alarm reset Always write 0 Reset register W only Note When reading SECR MINR HOURR DAYR DATER MONTHR YEARR of PAGE0 the current state is read Table 3 20 2 PAGE1 Alarm function registers Symbol Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Function Read Write SECR 1320H R W MINR 1321H 40 min 20 min 10 min 8 min 4 min 2 min 1 min Minute column R...

Page 501: ...ead 40 sec column 20 sec column 10 sec column 8 sec column 4 sec column 2 sec column 1 sec column 0 0 0 0 0 0 0 0 sec 0 0 0 0 0 0 1 1 sec 0 0 0 0 0 1 0 2 sec 0 0 0 0 0 1 1 3 sec 0 0 0 0 1 0 0 4 sec 0 0 0 0 1 0 1 5 sec 0 0 0 0 1 1 0 6 sec 0 0 0 0 1 1 1 7 sec 0 0 0 1 0 0 0 8 sec 0 0 0 1 0 0 1 9 sec 0 0 1 0 0 0 0 10 sec 0 0 1 1 0 0 1 19 sec 0 1 0 0 0 0 0 20 sec 0 1 0 1 0 0 1 29 sec 0 1 1 0 0 0 0 30 s...

Page 502: ...n 1 min column 0 0 0 0 0 0 0 0 min 0 0 0 0 0 0 1 1 min 0 0 0 0 0 1 0 2 min 0 0 0 0 0 1 1 3 min 0 0 0 0 1 0 0 4 min 0 0 0 0 1 0 1 5 min 0 0 0 0 1 1 0 6 min 0 0 0 0 1 1 1 7 min 0 0 0 1 0 0 0 8 min 0 0 0 1 0 0 1 9 min 0 0 1 0 0 0 0 10 min 0 0 1 1 0 0 1 19 min 0 1 0 0 0 0 0 20 min 0 1 0 1 0 0 1 29 min 0 1 1 0 0 0 0 30 min 0 1 1 1 0 0 1 39 min 1 0 0 0 0 0 0 40 min 1 0 0 1 0 0 1 49 min 1 0 1 0 0 0 0 50 ...

Page 503: ... o clock 0 1 0 0 0 0 10 o clock 0 1 1 0 0 1 19 o clock 1 0 0 0 0 0 20 o clock 1 0 0 0 1 1 23 o clock Note Do not set data other than as shown above 2 In case of 12 hour clock mode MONTHR MO0 0 7 6 5 4 3 2 1 0 Bit symbol HO5 HO4 HO3 HO2 HO1 HO0 HOURR 1322H Read Write R W Reset State Undefined Function 0 is read PM AM 10 hour column 8 hour column 4 hour column 2 hour column 1 hour column 0 0 0 0 0 0...

Page 504: ...ve 5 Day column register PAGE0 1 7 6 5 4 3 2 1 0 Bit symbol DA5 DA4 DA3 DA2 DA1 DA0 DATER 1324H Read Write R W Reset State Undefined Function 0 is read Day 20 Day 10 Day 8 Day 4 Day 2 Day 1 0 0 0 0 0 1 1st day 0 0 0 0 1 0 2nd day 0 0 0 0 1 1 3rd day 0 0 0 1 0 0 4th day 0 0 1 0 0 1 9th day 0 1 0 0 0 0 10th day 0 1 0 0 0 1 11th day 0 1 1 0 0 1 19th day 1 0 0 0 0 0 20th day 1 0 1 0 0 1 29th day 1 1 0...

Page 505: ...th 0 0 0 0 1 January 0 0 0 1 0 February 0 0 0 1 1 March 0 0 1 0 0 April 0 0 1 0 1 May 0 0 1 1 0 June 0 0 1 1 1 July 0 1 0 0 0 August 0 1 0 0 1 September 1 0 0 0 0 October 1 0 0 0 1 November 1 0 0 1 0 December Note Do not set data other than as shown above 7 Select 24 hour clock or 12 hour clock for PAGE1 only 7 6 5 4 3 2 1 0 Bit symbol MO0 MONTHR 1325H Read Write R W Reset State Undefined Function...

Page 506: ...ears 0 0 0 0 0 1 0 0 04 years 0 0 0 0 0 1 0 1 05 years 1 0 0 1 1 0 0 1 99 years Note Do not set data other than as shown above 9 Leap year register for PAGE1 only 7 6 5 4 3 2 1 0 Bit symbol LEAP1 LEAP0 YEARR 1326H Read Write R W Reset State Undefined Function 0 is read 00 leap year 01 one year after leap year 10 two years after leap year 11 three years after leap year 0 0 Current year is a leap ye...

Page 507: ...Select Page0 PAGE 1 Select Page1 0 Don t care ADJUST 1 Adjust sec counter When this bit is set to 1 the sec counter becomes to 0 when the value of the sec counter is 0 29 When the value of the sec counter is 30 59 the min counter is carried and sec counter becomes 0 Output Adjust signal during 1 cycle of fSYS After being adjusted once Adjust is released automatically PAGE0 only 11 Reset register f...

Page 508: ...ad correctly if reading data after 1Hz interrupt occurred 2 Using two times reading There is a possibility of incorrect clock data reading when the internal counter carries over To ensure correct data reading please read twice as follows Figure 3 20 2 Flowchart of clock data read Start END PAGER PAGE 0 Select PAGE0 Read the clock data 1st Read the clock data 2nd 1st data 2nd data NO YES ...

Page 509: ...ge counter inside the RTC which generate a 1Hz clock from 32 768 kHz The data is written after reset this counter However if clearing the counter it is counted up only first writing at half of the setting time first writing only Therefore if setting the clock counter correctly after clearing the counter set the 1Hz interrupt to enable And set the time after the first interrupt occurs at 0 5s is oc...

Page 510: ...y signal from a divider When the clock becomes enabled the carry signal is output to the clock the time is revised and operation continues However the clock is delayed when clock disabled state continues for one second or more Note that at this time system power is down while the clock is disabled In this case the clock is stopped and clock is delayed Figure 3 20 4 Flowchart of Clock disable Start...

Page 511: ...est is generated Setting alarm min alarm hour alarm date and alarm day is done by writing data to the relevant PAGE1 register When all setting contents correspond RTC generates an INTRTC interrupt if PAGER INTENA ENAALM is 1 However contents which have not been set up don t care state are always considered to correspond Contents which have already been set up cannot be returned independently to th...

Page 512: ... up PAGER ENAALM 0 RESTR DIS1HZ 0 DIS16HZ 1 RTC also generates an INTRTC interrupt on the falling edge of the clock 3 With 16Hz output clock RTC outputs a clock of 16Hz to ALARM pin by setting up PAGER ENAALM 0 RESTR DIS1HZ 1 DIS16HZ 0 RTC also generates INTRTC an interrupt on the falling edge of the clock ...

Page 513: ...z based on a low speed clock 32 768 kHz and outputs the signals from the MLDALM pin The melody tone can easily be heard by connecting an external loud speaker 2 Alarm generator The Alarm function generates eight kinds of alarm waveform having a modulation frequency 4096Hz determined by the low speed clock 32 768 kHz This waveform can be inverted by setting a value to a register The alarm tone can ...

Page 514: ...T IALM4E 0E 15bit conter UC1 8bit counter UC2 Alarm wave form generator ALM register Invert MELALMC ALMINV Selector ALMOUT MELOUT MELALMC FC1 0 Internal data bus Reset MELFH MELON Stop and Clear Low speed clock Invert MELOUT Alarm Generator Internal data bus Reset INTALM0 8192Hz INTALM1 512 Hz INTALM2 64 Hz INTALM3 2 Hz INTALM4 1 Hz MLDALM pin 4096 Hz Clear MELALMC MELALM INTALM ...

Page 515: ...e the free run counter is running FC1 0 is kept 01 MELFL register 7 6 5 4 3 2 1 0 bit Symbol ML7 ML6 ML5 ML4 ML3 ML2 ML1 ML0 Read Write R W Reset State 0 0 0 0 0 0 0 0 MELFL 1332H Function Setting melody frequency lower 8bit MELFH register 7 6 5 4 3 2 1 0 bit Symbol MELON ML11 ML10 ML9 ML8 Read Write R W R W Reset State 0 0 0 0 0 MELFH 1333H Function Control melody counter 0 Stop Clear 1 Start Set...

Page 516: ... then be set to 12 bit register MELFH MELFL The following are examples of settings and calculations of melody output frequency Formula for calculating melody waveform frequency fs 32 768 kHz Melody output waveform fMLD Hz 32768 2 N 4 Setting value for melody N 16384 fMLD 2 Note N 1 4095 001H FFFH 0 is not acceptable Example program When outputting an A musical note 440Hz LD MELALMC XXXXX1B Select ...

Page 517: ... MELALMC FC1 0 register and clear internal counter Alarm pattern must then be set on the 8 bit register of ALM If it is inverted output data set ALMINV as invert Then set the MELAMC FC1 0 to 11 to start the free run counter To stop the alarm output write 00H to the ALM register The following are examples of program setting value of alarm pattern and waveform of each setting value Setting value of ...

Page 518: ... ms 1 AL3 pattern once 250 ms AL8 pattern Once Modulation frequency 4096 Hz AL1 pattern Continuous output 31 25 ms 1 sec 1 2 8 1 AL2 pattern 8 times 1 sec 62 5 ms 1 sec 1 2 1 AL4 pattern Twice 1 sec 62 5 ms 1 sec 1 2 1 3 AL5 pattern 3 times 1 sec 62 5 ms 1 AL6 pattern 1 times 62 5 ms 1 2 AL7 pattern Twice ...

Page 519: ...AD 0 Note2 Setting ADMOD1 DACON 0 while the AD converter is in a stop can reduce current consumption Figure 3 22 1 ADC Block Diagram AD Monitor function interrupt INTADM Complete interrupt AD INTADHP Normal AD Conversion complete interrupt INTAD Comparator VREFH VREFL Sample Hold ADMOD1 Scan repeat Busy End Start Internal data bus Channel selection control circuit A D Conversion Result Register AD...

Page 520: ...ntrol Register 0 Normal conversion control 7 6 5 4 3 2 1 0 bit Symbol EOS BUSY I2AD ADS HTRGE TSEL1 TSEL0 Read Write R R W Reset State 0 0 0 0 0 0 0 ADMOD0 12B8H Function Normal AD conversion end flag 0 During conversion sequence or before starting 1 Complete conversion sequence Normal AD conversion BUSY Flag 0 Stop conversion 1 During conversion AD conversion when IDLE2 mode 0 Stop 1 Operate Star...

Page 521: ...er Next SCAN start timing control for the channel scan repeat mode Channel Scan Repeat mode SCAN 1 REPEAT 1 0 No Wait 1 Start after read last of conversion result store Register Specify AD conversion interrupt for Channel Fixed Repeat Conversion mode Channel Fixed Repeat Conversion Mode SCAN 0 REPEAT 1 0 Generates interrupt every conversion 1 Generated interrupt every fourth conversion DAC VREF ap...

Page 522: ...n Always read as 0 Top priority AD conversion at Hard ware trigger 0 Disable 1 Enable Select Hard ware trigger 00 INTTB10 interrupt 01 Reserved 10 ADTRG 11 I 2 S Sampling Counter Output AD Mode Control Register 3 Top priority conversion control 7 6 5 4 3 2 1 0 bit Symbol HADCH2 HADCH1 HADCH0 Read Write R W R W Reset State 0 0 0 0 0 ADMOD3 12BBH Function Always write 0 Top priority analog input cha...

Page 523: ... 0 0 ADMOD5 12BDH Function Select analog channel for AD monitor function 1 000 AN0 100 AN4 001 AN1 101 AN5 010 AN2 110 Reserved 011 AN3 111 Reserved Select analog channel for AD monitor function 0 000 AN0 100 AN4 001 AN1 101 AN5 010 AN2 110 Reserved 011 AN3 111 Reserved Note1 When converting AD in hard ware trigger by setting HHTRGE and HTRGE to 1 set PGFC PG3F to 1 as ADTRG in case of external TR...

Page 524: ...ore Lower 2 bits of AN1 AD conversion result Overrun flag 0 No generate 1 Generate AD conversion result store flag 1 Stored AD Conversion Result Register 1 High 7 6 5 4 3 2 1 0 bit Symbol ADR19 ADR18 ADR17 ADR16 ADR15 ADR14 ADR13 ADR12 Read Write R Reset State 0 0 0 0 0 0 0 0 ADREG1H 12A3H Function Store Upper 8 bits of AN1 AD conversion result 9 8 7 6 5 4 3 2 1 0 Channel X conversion result 7 6 5...

Page 525: ...ore Lower 2 bits of AN3 AD conversion result Overrun flag 0 No generate 1 Generate AD conversion result store flag 1 Stored AD Conversion Result Register 3 High 7 6 5 4 3 2 1 0 bit Symbol ADR39 ADR38 ADR37 ADR36 ADR35 ADR34 ADR33 ADR32 Read Write R Reset State 0 0 0 0 0 0 0 0 ADREG3H 12A7H Function Store Upper 8 bits of AN3 AD conversion result 9 8 7 6 5 4 3 2 1 0 Channel X conversion result 7 6 5...

Page 526: ...ore Lower 2 bits of AN5 AD conversion result Overrun flag 0 No generate 1 Generate AD conversion result store flag 1 Stored AD Conversion Result Register 5 High 7 6 5 4 3 2 1 0 bit Symbol ADR59 ADR58 ADR57 ADR56 ADR55 ADR54 ADR53 ADR52 Read Write R ADREG5H 12ABH Reset State 0 0 0 0 0 0 0 0 Function Store Upper 8 bits of AN5 AD conversion result 9 8 7 6 5 4 3 2 1 0 Channel X conversion result 7 6 5...

Page 527: ...3 ADRSP2 Read Write R Reset State 0 0 0 0 0 0 0 0 ADREGSPH 12B1H Function Store Upper 8 bits of an AD conversion result 9 8 7 6 5 4 3 2 1 0 Channel X conversion result 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Figure 3 22 9 AD Conversion Registers ADREGxH ADREGxL Bits 5 2 are always read as 0 Bit 0 is the AD conversion result store flag ADRxRF When AD conversion result is stored the flag is set to 1 When Lo...

Page 528: ...AD conversion result compare criterion AD Conversion Result Compare Criterion Register 1 Low 7 6 5 4 3 2 1 0 bit Symbol ADR21 ADR20 Read Write R W Reset State 0 0 ADCM1REGL 12B6H Function Store Lower 2 bits of an AD conversion result compare criterion AD Conversion Result Compare Criterion Register 1 High 7 6 5 4 3 2 1 0 bit Symbol ADR29 ADR28 ADR27 ADR26 ADR25 ADR24 ADR23 ADR22 Read Write R W Res...

Page 529: ...executed at the clock frequency selected in the above register To assure conversion accuracy however the conversion clock frequency must not exceed 12MHz Note2 Don t change the clock frequency while AD conversion is in progress Figure 3 22 11 AD Conversion Registers fIO fSYS 2 ADCLK2 0 ADCLK AD conversion speed 100 fIO 4 10 0MHZ 12 μsec 40MHz 101 fIO 5 8MHZ 15 μsec 011 fIO 3 10 0MHZ 12 μsec 30MHz ...

Page 530: ...mode select one channel from the AN0 to AN5 pins by setting ADMOD1 SCAN 0 ADMOD1 ADCH2 0 When using an analog input channel in scan mode select one scan mode from the six scan modes by setting ADMOD1 SCAN 1 ADMOD1 ADCH2 0 2 For top priority AD conversion Select one channel from the analog input pins AN0 to AN5 by setting ADMOD3 HADCH2 0 After reset ADMOD1 SCAN is initialized to 0 and ADMOD1 ADCH2 ...

Page 531: ...y supports Fixed Channel Single Conversion mode The ADMOD0 TSEL1 0 and ADMOD2 HTSEL1 0 enable a hardware trigger for a normal and Top priority AD conversion respectively When these bits are set to 10 a normal or Top priority AD conversion is triggered by a falling edge applied to ADTRG pin When ADMOD0 TSEL1 0 is set to 00 a normal AD conversion is triggered by INTTB00 of 16 Bit Timer interrupt Whe...

Page 532: ... ware trigger occurs the ADC aborts any ongoing conversion immediately and then start a Top priority AD conversion for the channel specified by ADMOD3 HADCH2 0 Upon the completion of the Top priority conversion the ADC stores the conversion result to ADREGSPH L and then resumes the suspended normal conversion with that channel Note It cannot overlap with three or more AD conversions Prohibition ex...

Page 533: ... conversion mode Setting ADMOD1 REPEAT SCAN to 01 selects the channel scan single conversion mode This mode performs a conversion only one time at each scan channel selected After scan conversion ends ADMOD0 EOS is set to 1 generating Normal AD conversion End interrupt request EOS is cleared to 0 only by being read c Channel fix repeat conversion mode Setting ADMOD1 REPEAT SCAN to 10 selects the c...

Page 534: ...itching to standby mode 2 Top priority AD conversion The operation mode is only single conversion by channel fix mode The settings in ADMOD1 REPEAT SCAN are not involved When startup conditions are established a conversion at a channel specified by ADMOD3 HADCH2 0 is performed only one time When conversion ends the top priority AD conversion end interrupt INTADHP is generated which sets 1 in ADMOD...

Page 535: ... enables the AD monitoring function The value of Result storage register that is appointed by ADMOD5 is compared with the value of AD conversion result register H L ADMOD4 CMP1C 0C can select greater or smaller of comparison format As register ADMOD4 IRQEN1 0 is Enable This comparison operation is performed each time when a result is stored in the corresponding conversion result storage register W...

Page 536: ...nce between analog input channels and AD conversion result registers AD Conversion result registers Analog input channel Port G Other conversion modes than shown in the right Channel fix repeat conversion mode per 4 times AN0 ADREG0H L AN1 ADREG1H L AN2 ADREG2H L AN3 ADREG3H L AN4 ADREG4H L AN5 ADREG5H L ADREG0H L ADREG3H L ADREG1H L ADREG2H L Note In order to detect overruns without omission read...

Page 537: ...DAC On ADMOD3 0 0 1 0 0 0 0 0 Set pin AN2 to be the analog input channel ADMOD2 0 0 0 0 1 0 0 0 Start a Top priority AD conversion by software Interrupt routine processing example WA ADREGSP Read value of ADREGSPL and ADREGSPH into 16 bits general purpose register WA WA 6 Shift contents read into WA six times to right and zero fill upper bits 2A00H WA Write contents of WA to memory address 2A00H 4...

Page 538: ...ng the watchdog timer output to the reset pin internally forces a reset The level of external RESET pin is not changed 3 23 1 Configuration Figure 3 23 1 is a block diagram of the watchdog timer WDT Figure 3 23 1 Block Diagram of Watchdog Timer Note Care must be exercised in the overall design of the apparatus since the watchdog timer may fail to function correctly due to external noise etc WDMOD ...

Page 539: ...r STOP mode The watchdog timer counter continues counting during bus release when BUSAK goes low When the device is in IDLE2 mode the operation of WDT depends on the WDMOD I2WDT setting Ensure that WDMOD I2WDT is set before the device enters IDLE2 mode The watchdog timer consists of a 22 stage binary counter which uses the clock fIO as the input clock The binary counter can output 215 fIO 217 fIO ...

Page 540: ...ed state merely by setting WDTE to 1 3 Watchdog timer out reset connection RESCR This register is used to connect the output of the watchdog timer with the RESET terminal internally Since WDMOD RESCR is initialized to 0 at reset a reset by the watchdog timer will not be performed 2 Watchdog timer control register WDCR This register is used to disable and clear the binary counter for the watchdog t...

Page 541: ...ion Watchdog timer detection time 00 2 15 fIO Approximately 819 2 μs at fIO 40 MHz 01 2 17 fIO Approximately 3 276 ms at fIO 40 MHz 10 2 19 fIO Approximately 13 107 ms at fIO 40 MHz 11 2 21 fIO Approximately 52 428 ms at fIO 40 MHz Watchdog timer enable disable control 0 Disabled 1 Enabled Figure 3 23 4 Watchdog Timer Mode Register 7 6 5 4 3 2 1 0 Bit symbol WDCR 1301H Read Write W Reset State Fun...

Page 542: ...YS 3 24 1 1 Control Register The control register is used to control the operation of the MAC MAC Control Register 7 6 5 4 3 2 1 0 bit Symbol MOVF MOPST MSTTG2 MSTTG1 MSTTG0 MSGMD MOPMD1 MOPMD0 Read Write R W W R W Reset State 0 0 0 0 0 0 0 0 MACCR 1BFCH A read modify write operation cannot be performed Function Overflow flag 0 No overflow 1 Overflow occurred Calculation soft start 0 Don t care 1 ...

Page 543: ...gisters Note 3 All the registers can be accessed in long word word or byte units In case of using sign mode it can be accessed in long word only Note 4 When MACCR MSTTG2 0 is set to 0 001 010 or 011 and the registers are written in word or byte units the 7 0 bits of each register must be written last Note 5 The MACORL register is fixed one system clock fSYS after calculation is started and the MAC...

Page 544: ...nts of the MACOR register Then the result is stored back in the MACOR register b 64 32 32 mode In this mode the contents of the MACMA register and the MACMB register are multiplied and the result is subtracted from the contents of the MACOR register Then the result is stored back in the MACOR register c 32 32 64 mode In this mode the contents of the MACMA register and the MACMB register are multip...

Page 545: ...ible to set signed two s complement data in the MACOR register to perform additions and subtractions in signed mode In case of using sign mode MACCR MSGMD 1 it must need to write to MACMA and MACMB register with longword 32bit 2 Calculation start trigger As a trigger to start calculation writing to the MACMA MACMB or MACOR register or soft start MACCR MOPST 1 can be selected in MACCR MSTTG2 0 3 Ov...

Page 546: ...DDDDDE 22222222 ld MACORL xhl Write 33333333 to MACORL ld MACORH xde Clear MACORH ld MACMA xix Write 11111111 to MACMA ld MACMB xiy Write 22222222 to MACMB set 5 MACCR ld xhl MACORL Read lower result 0x41FDB975 bit 7 MACCR Check over flow error jp nz ERROR Go to error routine if there is over flow error ld xde MACORH Read upper result 0x02468ACF 3 Unsigned multiply accumulate operation two multipl...

Page 547: ...REFL maximum ratings for AVCC is applied Note3 The absolute maximum ratings are rated values that must not be exceeded during operation even for an instant Any one of the ratings must not be exceeded If any absolute maximum rating is exceeded a device may break down or its performance may be degraded causing it to catch fire or explode resulting in injury to the user Thus when designing products t...

Page 548: ...71 to P76 P90 PC4 to PC7 PF0 to PF5 PG0 to PG5 PJ5 to PJ6 PN0 to PN7 PR0 to PR3 PT0 to PT7 PX5 0 3 DVCC3A 3 0 DVCC3A 3 6 VIL1 Input Low Voltage for PV6 to PV7 0 3 DVCC3A 3 0 DVCC3A 3 6 VIL2 Input Low Voltage for P91 to P92 P96 to P97 PA0 to PA7 PC0 to PC3 PP3 to PP5 RESET 0 25 DVCC3A 3 0 DVCC3A 3 6 VIL3 Input Low Voltage for AM0 to AM1 0 1 DVCC3A 3 0 DVCC3A 3 6 VIL4 Input Low Voltage for X1 0 1 DV...

Page 549: ... 7 DVCC3A DVCC3A 0 3 3 0 DVCC3A 3 6 VIH1 Input High Voltage for PV6 to PV7 0 7 DVCC3A DVCC3A 0 3 3 0 DVCC3A 3 6 VIH2 Input High Voltage for P91 to P92 P96 to P97 PA0 to PA7 PC0 to PC3 PP3 to PP5 RESET 0 75 DVCC3A DVCC3A 0 3 3 0 DVCC3A 3 6 VIH3 Input High Voltage for AM0 to AM1 0 9 DVCC3A DVCC3A 0 3 3 0 DVCC3A 3 6 VIH4 Input High Voltage for X1 0 9 DVCC1C DVCC1C 0 3 1 4 DVCC1C 1 6 VIH5 Input High V...

Page 550: ... IOH 0 5mA 3 0 DVCC3A VOH2 Output High Voltage2 Except VOL1 output pin 2 4 V IOH 2mA 3 0 DVCC3A IMon Internal resistor ON MX MY pins 30 VOL 0 2V IMon Internal resistor ON PX PY pins 30 Ω VOH VCC 0 2V VCC 3 0 to 3 6 V ILI Input Leakage Current 0 02 5 μA 0 0 Vin DVCC3A ILO Output Leakage Current 0 05 10 μA 0 2 Vin DVCC3A 0 2V RRST Pull Up Down Resistor for RESET PA0 to PA7 P96 30 50 70 kΩ CIO Pin Ca...

Page 551: ...3200 PLL_OFF fSYS 10MHz DVCC1A 1B 1C 1 6V 35 Ta 70 C 6 30 Ta 50 C DVCC3A 3 6V AVCC 3 6V 800 Ta 70 C ICC STOP 200 600 μA Ta 50 C DVCC1A 1 6V DVCC1B 1 6V DVCC1C 1 6V XT OFF X OFF Note1 Typical values are value that when Ta 25 C and VCC 3 3 V DVCC1A 1B 1C 1 5V unless otherwise noted Note2 ICC measurement conditions NORMAL SLOW All functions are operational output pins except bus pin are open and inpu...

Page 552: ...8 0 7 15 3 tAD4 6 0T 18 0 57 82 5 2 A0 to A23 valid D0 to D31 input at 4 waits 6 waits tAD6 8 0T 18 0 82 115 6 1 RD falling D0 to D31 input at 0 waits tRD 1 5T 18 0 0 75 7 tRD4 5 5T 18 0 50 75 73 6 6 2 RD falling D0 to D31 input at 4 waits 6 waits tRD6 7 5T 18 0 75 75 106 5 7 1 RD low width at 0 waits tRR 1 5T 10 8 75 14 9 tRR4 5 5T 10 58 75 81 3 7 2 RD low width at 4 waits 6 waits tRR6 7 5T 10 83...

Page 553: ...2 RD rising D0 to D31 output tRDO 0 5T 1 0 5 25 7 3 23 1 Write width for SRAM at 0 waits tSWP 1 0T 4 0 8 5 12 6 tSWP2 3 0T 4 0 33 5 45 8 23 2 Write width for SRAM at 2 waits 4 waits tSWP4 5 0T 4 0 58 5 79 0 24 1 Data byte control end of write for SRAM at 0 waits tSBW 1 0T 4 0 8 5 12 6 tSBW2 3 0T 4 0 33 5 45 8 24 2 Data byte control end of write for SRAM at 2 waits 4 waits tSBW4 5 0T 4 0 58 5 79 0 ...

Page 554: ...ignals is undefined Note2 The above timing chart show an example of basic bus timing The CSn R W RD WRxx SRxxB SRWR pins timing can be adjusted by memory controller timing adjust function tOSC SDCLK WAIT A0 to A23 D0 to D31 SRxxB X1 CSn RD SRWR tCL tCYC tCH tTK tKT tAD tRR tRD tRRH tAR tRK tSBA Data input tHA tHR R W ...

Page 555: ...efined Note2 The above timing chart show an example of basic bus timing The CSn R W RD WRxx SRxxB SRWR pins timing can be adjusted by memory controller timing adjust function tOSC SDCLK WAIT A0 to A23 D0 to D31 SRxxB X1 CSn WRxx SRWR tCL tCYC tCH tTK tKT tWW tDW tAW tWK tSBW Data output tWA tSWR tWD RD tRDO tSDH tSAS tSWP tSDS R W ...

Page 556: ...F30 2009 06 12 92CF30 554 3 Read cycle 1 wait 4 Write cycle 1 wait SDCLK Data input tRR3 tAD3 tRD3 WAIT A0 to A23 CSn RD D0 to D31 R W SDCLK Data output tWW3 tDW3 WAIT A0 to A23 CSn WRxx D0 to D31 RD R W tRDO ...

Page 557: ...lid D0 to D31 hold tHA 0 0 0 6 RD rising D0 to D31 hold tHR 0 0 0 ns AC measuring condition Note The a b and c of Symbol in above table depend on the falling timing of RD pin The falling timing of RD pin is set by MEMCR0 RDTMG1 0 in memory controller If MEMCR0 RDTMG1 0 is set to 00 it correspond with a in above table and 01 is b 10 is c Page Mode Access Timing when using a 16 byte page size exampl...

Page 558: ...5 6 10 1 11 Data hold time from internal read tHR 0 0 0 1Word Single tDS 0 5T 4 2 25 4 3 12 Data set up time Burst tDS 0 5T 4 2 25 4 3 1Word Single tDH T 10 2 5 6 6 13 Data hold time Burst tDH 0 5T 4 2 25 4 3 14 Address set up time tAS 0 5T 4 2 25 4 3 15 Address hold time tAH 0 5T 4 2 25 4 3 16 CKE set up time tCKS 0 5T 3 3 25 5 3 17 Command set up time tCMS 0 5T 3 3 25 5 3 18 Command hold time tC...

Page 559: ... 557 1 SDRAM read timing 1Word length read mode SPRE 1 Column Row SDCLK SDxxDQM SDCS SDRAS SDCAS A0 to A9 D0 to D15 SDWE A10 A11 to A15 tCH tCL tCK tRCD tRAS tRP tCMS tCMH tCMS tCMH tRRD tAH tAS tAS tAH Row Row Data input tAC tHR ...

Page 560: ...558 2 SDRAM write timing Single write mode SPRE 1 SDCLK SDxxDQM SDCS SDRAS SDCAS D0 to D15 SDWE tCH tCL tCK tWR tRCD tRP tCMS tRRD tCMS tCMH tRAS Data output tDS tDH tCMH Column Row A0 to A9 A10 A11 to A15 tAH tAS tAS tAH Row Row ...

Page 561: ...st read timing Start burst cycle Column Row SDCLK SDxxDQM SDCS SDRAS SDCAS A0 to A9 D0 to D15 SDWE A10 A11 to A15 tCK tRCD tCMS tCMH tCMH tAH tAS Row Row Data input tAC tCMH tCMS tCMS 027 tAH tAS tAS 0 tAC tAC Data input Data input tHR tHR tMRD ...

Page 562: ...06 12 92CF30 560 4 SDRAM burst read timing End burst timing SDCLK SDxxDQM SDCS SDRAS SDCAS D0 to D15 SDWE tCK tRP tCMS tCMH Data input tCMH tCMS tCMS Column tAC Data input tHR tHR tCMH Row A0 to A9 A10 A11 to A15 tAS ...

Page 563: ...TMP92CF30 2009 06 12 92CF30 561 5 SDRAM initializes timing 220 SDCLK SDxxDQM SDCS SDRAS SDCAS A0 to A9 SDWE tCK tRC tCMS tCMH tCMS tCMH tCMH tCMS A10 A11 to A15 tAS tAH tCMH tCMS 0 ...

Page 564: ...92CF30 2009 06 12 92CF30 562 6 SDRAM refreshes timing 7 SDRAM self refresh timing SDCLK SDxxDQM SDCS SDRAS SDCAS SDWE tCK tRC tCMH tCMS SDCLK SDCKE SDCS SDRAS SDCAS SDWE tCK tRC tCMH tCMS tCKS tCKS SDxxDQM ...

Page 565: ... 47 6 tDS Write data setup time 1 0 n T 20 30 47 7 tDH Write data hold time 0 5 m T 2 42 56 ns AC measuring condition Note1 The n in Variable means wait number which is set to NDFMCR0 SPLW1 0 and m means number which is set to NDFMCR0 SPHW1 0 Example If NDFMCR0 SPLW1 0 is set to 01 n 1 tRP 1 5 n T 12 2 5T 12 Note2 In above variable the setting that result is minus can not use Data input SDCLK A0 t...

Page 566: ... valid SCLK rising falling tRDS 20 20 20 ns 2 SCLK output mode I O interface mode Variable Parameter Symbol Min Max 80 MHz 60 MHz Unit SCLK cycle Programmable tSCY 16T 8192T 200 266 Output data SCLK rising falling tOSS tSCY 2 40 60 93 SCLK rising falling Output data hold tOHS tSCY 2 40 60 93 SCLK rising falling Input data hold tHSR 0 0 0 SCLK rising falling Input data valid tSRD tSCY 1T 50 137 5 1...

Page 567: ...rupt operation Variable Parameter Symbol Min Max 80 MHz 60 MHz Unit INT0 INT7 low width tINTAL 2T 40 65 74 INT0 INT7 high width tINTAH 2T 40 65 74 ns 4 3 8 USB Timing Full speed DVCCA 3 3 0 3 V fUSB 48 MHz Parameter Symbol Min Max Unit D D rising time tR 4 20 D D falling time tF 4 20 ns Output signal crossover voltage VCRS 1 3 2 0 V AC measuring condition D D TMP92CF30 R1 27 Ω R1 27 Ω R2 15 kΩ CL ...

Page 568: ... 0 5 tCR 15 35 35 I2SCKO low width tLB 0 5 tCR 15 35 35 I2SDO I2SWS setup time tSD 0 5 tCR 15 35 35 I2SDO I2SWS hold time tHD 0 5 tCR 8 42 42 ns Note The Maximum operation frequency of I2SCKO in I 2 S circuit is 10MHz Don t set I2SCKO to value more than 10MHz AC measuring condition I2SCKO I2SDO and I2SWS pins CL 30 pF I2SCKO tCR tLB tHB I2SDO tHD tHD tSD I2SWS ...

Page 569: ...PCLK rising falling tODS 0 5S 18 7 15 SPCLK rising falling Output data hold tODH 0 5S 10 15 23 4 Input data valid SPCLK rising falling tIDS 5 5 5 SPCLK rising falling Input data valid tIDH 5 5 5 ns AC measuring condition Clock of top column in above table shows system clock frequency and S in Variable show SPCLK clock cycle ns CL 25 pF SPCLK output at SPIMD TCPOL RCPOL 11 SPDO output fPP tr tf 0 2...

Page 570: ...S DVSS Analog input voltage AVIN VREFL VREFH V IREFON VREFON 1 0 38 0 45 mA Analog current for analog reference voltage IREFOFF VREFON 0 1 5 μA Total error Quantize error of 0 5 LSB is included ET Conversion speed at 12μs 2 0 4 0 LSB Note1 1 LSB VREFH VREFL 1024 V Note2 Minimum frequency for operation Minimum clock for AD converter operate is 3MHz Clock frequency that is seleted by Clock gear fSYS...

Page 571: ...e is a possibility of operating error when using C1 and C2 values in the table below When designing the board design the minimum length pattern around the oscillator We also recommend that oscillator evaluation be carried out using the actual board 1 Connection example 2 Recommended ceramic oscillator TMP92CF30 recommends the high frequency oscillator by Murata Manufacturing Co Ltd Please refer to...

Page 572: ...ress 7 6 1 0 Bit Symbol Read Write Initial value after system reset Remarks Note Prohibit RMW in the table means that you cannot use RMW instructions on these register Example When setting bit0 only of the register PxCR the instruction SET 0 PxCR cannot be used The LD transfer instruction must be used to write all eight bits Read Write R W Both read and write are possible R Only read is possible W...

Page 573: ...FC BH CH CH P7 CH CH PF DH DH DH DH EH EH P7CR EH EH PFCR FH FH P7FC FH FH PFFC Address Name Address Name Address Name Address Name 0040H PG 0050H PK 0060H PP 0070H Reserved 1H 1H 1H PPFC2 1H Reserved 2H 2H 2H PPCR 2H Reserved 3H PGFC 3H Reserved 3H PPFC 3H Reserved 4H 4H PL 4H PR 4H Reserved 5H 5H PLFC2 5H 5H Reserved 6H 6H PLCR 6H PRCR 6H Reserved 7H 7H PLFC 7H PRFC 7H Reserved 8H 8H PM 8H 8H Re...

Page 574: ... PXFC2 2H 2H 2H PTCR 2H PXCR 3H 3H PJDR 3H PTFC 3H PXFC 4H P4DR 4H PKDR 4H 4H 5H P5DR 5H PLDR 5H 5H 6H P6DR 6H PMDR 6H 6H 7H P7DR 7H PNDR 7H 7H 8H P8DR 8H PPDR 8H PV 8H 9H P9DR 9H PRDR 9H PVFC2 9H AH PADR AH AH PVCR AH BH BH PTDR BH PVFC BH CH PCDR CH CH CH DH DH PVDR DH DH EH EH EH EH FH PFDR FH PXDR FH FH Note Do not access no allocated name address ...

Page 575: ...8H DMAB 9H INTETB1 9H INTEKEY 9H 9H DMAR AH AH Reserved AH IIMC1 AH DMASEL BH INTES0 BH INTEI2S0 BH BH CH INTES1 CH INTENDFC CH CH DH DH Reserved DH DH EH EH INTEP0 EH EH FH FH INTEAD FH Reserved FH 3 MEMC 4 TSI Address Name Address Name Address Name Address Name 0140H B0CSL 0150H 0160H 01F0H TSICR0 1H B0CSH 1H 1H 1H TSICR1 2H MAMR0 2H 2H 2H Reserved 3H MSAR0 3H 3H 3H 4H B1CSL 4H 4H 4H 5H B1CSH 5H...

Page 576: ...Reserved 2H Reserved 2H 3H Reserved 3H Reserved 3H 3H 4H Reserved 4H Reserved 4H Reserved 4H 5H Reserved 5H Reserved 5H Reserved 5H 6H Reserved 6H Reserved 6H Reserved 6H 7H Reserved 7H Reserved 7H 7H 8H Reserved 8H Reserved 8H Reserved 8H 9H Reserved 9H Reserved 9H Reserved 9H AH Reserved AH AH Reserved AH BH Reserved BH BH Reserved BH CH Reserved CH CH Reserved CH DH Reserved DH DH Reserved DH E...

Page 577: ...E BH EP3_SIZE_L_A BH EP3_SIZE_H_A CH CH CH DH DH DH EH EH EH FH FH FH Address Name Address Name Address Name 07B0H 07C0H bmRequestType 07D0H COMMAND 1H EP1_SIZE_H_B 1H bRequest 1H EPx_SINGLE1 2H EP2_SIZE_H_B 2H wValue_L 2H Reserved 3H EP3_SIZE_H_B 3H wValue_H 3H EPx_BCS1 4H 4H wIndex_L 4H Reserved 5H 5H wIndex_H 5H Reserved 6H 6H wLength_L 6H INT_Control 7H 7H wLength_H 7H Reserved 8H 8H SetupRece...

Page 578: ...NTFR1 1H FRAME_L 1H USBINTFR2 2H FRAME_H 2H USBINTFR3 3H ADDRESS 3H USBINTFR4 4H Reserved 4H USBINTMR1 5H Reserved 5H USBINTMR2 6H USBREADY 6H USBINTMR3 7H Reserved 7H USBINTMR4 8H Set Descriptor STALL 8H USBCR1 9H 9H AH AH BH BH CH CH DH DH EH EH FH FH Note Do not access no allocated name address ...

Page 579: ... LOCALPX 1H LOCALRX 1H LOCALESX 1H LOCALOSX 2H LOCALPY 2H LOCALRY 2H LOCALESY 2H LOCALOSY 3H LOCALPY 3H LOCALRY 3H LOCALESY 3H LOCALOSY 4H LOCALPZ 4H LOCALRZ 4H LOCALESZ 4H LOCALOSZ 5H LOCALPZ 5H LOCALRZ 5H LOCALESZ 5H LOCALOSZ 6H 6H 6H 6H 7H 7H 7H 7H 8H Reserved 8H LOCALWX 8H LOCALEDX 8H LOCALODX 9H Reserved 9H LOCALWX 9H LOCALEDX 9H LOCALODX AH Reserved AH LOCALWY AH LOCALEDY AH LOCALODY BH Rese...

Page 580: ...2H NDFMCR1 2H NDRSCD0 2H NDFDTR1 3H NDFMCR1 3H 3H NDFDTR1 4H NDECCRD0 4H NDRSCA1 4H 5H NDECCRD0 5H NDRSCA1 5H 6H NDECCRD1 6H NDRSCD1 6H 7H NDECCRD1 7H 7H 8H NDECCRD2 8H NDRSCA2 8H 9H NDECCRD2 9H NDRSCA2 9H AH NDECCRD3 AH NDRSCD2 AH BH NDECCRD3 BH BH CH NDECCRD4 CH NDRSCA3 CH DH NDECCRD4 DH NDRSCA3 DH EH EH NDRSCD3 EH FH FH FH Note Do not access no allocated name address ...

Page 581: ...H HDMACA1 9H HDMACA2 9H HDMACA3 AH HDMACB0 AH HDMACB1 AH HDMACB2 AH HDMACB3 BH HDMACB0 BH HDMACB1 BH HDMACB2 BH HDMACB3 CH HDMAM0 CH HDMAM1 CH HDMAM2 CH HDMAM3 DH DH DH DH EH EH EH EH FH FH FH FH Address Name Address Name Address Name 0940H HDMAS4 0950H HDMAS5 0970H 1H HDMAS4 1H HDMAS5 1H 2H HDMAS4 2H HDMAS5 2H 3H 3H 3H 4H HDMAD4 4H HDMAD5 4H 5H HDMAD4 5H HDMAD5 5H 6H HDMAD4 6H HDMAD5 6H 7H 7H 7H ...

Page 582: ...EH FH FH FH 13 16 bit timer 14 SIO 15 SBI Address Name Address Name Address Name Address Name 1180H TB0RUN 1190H TB1RUN 1200H SC0BUF 1240H SBICR1 1H 1H 1H SC0CR 1H SBIDBR 2H TB0MOD 2H TB1MOD 2H SC0MOD0 2H I2CAR 3H TB0FFCR 3H Reserved 3H BR0CR 3H SBICR2 SBISR 4H 4H 4H BR0ADD 4H SBIBR0 5H 5H 5H SC0MOD1 5H 6H 6H 6H 6H 7H 7H 7H SIR0CR 7H SBICR0 8H TB0RG0L 8H TB1RG0L 8H SC1BUF 8H 9H TB0RG0H 9H TB1RG0H ...

Page 583: ...EGL 6H 7H ADREG3H 7H ADCM1REGH 7H 8H ADREG4L 8H ADMOD0 8H 9H ADREG4H 9H ADMOD1 9H AH ADREG5L AH ADMOD2 AH BH ADREG5H BH ADMOD3 BH CH Reserved CH ADMOD4 CH DH Reserved DH ADMOD5 DH EH Reserved EH EH FH Reserved FH ADCCLK FH 18 RTC 19 MLD Address Name Address Name 1320H SECR 1330H ALM 1H MINR 1H MELALMC 2H HOURR 2H MELFL 3H DAYR 3H MELFH 4H DATER 4H ALMINT 5H MONTHR 5H 6H YEARR 6H 7H PAGER 7H 8H RES...

Page 584: ... 2H MACMA 2H 3H 3H 3H MACMA 3H 4H 4H 4H MACMB 4H 5H 5H 5H MACMB 5H 6H 6H 6H MACMB 6H 7H 7H 7H MACMB 7H 8H I2S0CTL 8H Reserved 8H MACORL 8H 9H I2S0CTL 9H Reserved 9H MACORL 9H AH I2S0C AH Reserved AH MACORL AH BH I2S0C BH Reserved BH MACORL BH CH CH CH MACORH CH MACCR DH DH DH MACORH DH EH EH EH MACORH EH FH FH FH MACORH FH Note Do not access no allocated name address ...

Page 585: ...l port Output latch register is set to 1 1 P87 P86 P83 P82 P81 P80 R W R W P8 PORT8 0020H 1 1 1 0 Note 1 1 P97 P96 P92 P91 P90 R R W P9 PORT9 0024H Data from external port Data from external port Output latch register is set to 1 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 R PA PORTA 0028H Data from external port PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 R W PC PORTC 0030H Data from external port Output latch register ...

Page 586: ...PORTP 0060H 0 Data from external port Output latch register is cleared to 0 PR3 PR2 PR1 PR0 R W PR PORTR 0064H Data from external port Output latch register is cleared to 0 PT7 PT6 PT5 PT4 PT3 PT2 PT1 PT0 R W PT PORTT 00A0H Data from external port Output latch register is cleared to 0 PV7 PV6 R W PV PORTV 00A8H Data from external port Output latch register is cleared to 0 PX5 PX4 R W PX PORTX 00B0...

Page 587: ... W 0 0 0 0 0 0 0 0 P6CR PORT6 control register 001AH Prohibit RMW 0 Input 1 Output P67F P66F P65F P64F P63F P62F P61F P60F W 1 1 1 1 1 1 1 1 P6FC PORT6 function register 001BH Prohibit RMW 0 Port 1 Address bus A16 A23 P76C P75C P74C P73C P72C P71C W 0 0 0 0 0 0 P7CR PORT7 control register 001EH Prohibit RMW 0 Input port WAIT 1 Output port 0 Input port NDR B 1 Output port R W 0 Input port 1 Output ...

Page 588: ...rol register 0026H Prohibit RMW 0 Input port 1 0 CTS SCLK0 1 1 Output port SCLK0 1 0 Input port RXD0 1 1 Output port 0 Input port 1 Output port TXD0 1 P96F P92F P90F W W W 0 0 0 P9FC PORT9 function register 0027H Prohibit RMW 0 Input port 1 INT4 0 Port 1 0 CTS 1 SCLK0 0 Port 1 TXD0 1 P95F2 P94F2 P93F2 P90FC2 W W W W 0 0 0 0 0 0 P9FC2 PORT9 function register2 0025H Prohibit RMW Always write 0 P92 S...

Page 589: ...tion register 0033H Prohibit RMW 0 Port 1 KO output Open Drain 0 Port 1 EA28 SPCLK output 0 Port 1 EA27 SPDO output 0 Port 1 EA26 SPDI input 0 Port 1 INT3 TA2IN 0 Port 1 INT2 0 Port 1 INT1 TA0IN 0 Port 1 INT0 PC4F2 W 0 PCFC2 PORTC function 2 register 0031H Prohibit RMW SPDI selection 0 PR0 1 PC4 PF2C PF1C PF0C W 0 0 0 PFCR PORTF control register 003EH Prohibit RMW 0 Input 1 Output PF7F PF2F PF1F P...

Page 590: ...H Prohibit RMW 0 Input 1 Output PL7F PL6F PL5F PL4F PL3F PL2F PL1F PL0F W 0 0 0 0 0 0 0 0 PLFC PORTL function register 0057H Prohibit RMW 0 Port 1 Don t setting PL0F2 W 0 1 PLFC2 PORTL function register 2 0055H Prohibit RMW 0 Port 1 Data bus D16 to D23 PM7F PM2F PM1F W W 0 0 0 PMFC PORTM function register 005BH Prohibit RMW 0 Port 1 Don t setting 0 Port 1 ALARM at PM2 1 MLDALM at PM2 0 0 Port 1 ML...

Page 591: ...on 0 Others 1 SCLK CTS inpu t or SCLK output PP4 selection 0 Others 1 RXD input PP3 selection 0 Others 1 TXD output PP3 selection 0 CMOS 1 Open drain PR3C PR2C PR1C PR0C W 0 0 0 0 PRCR PORTR control register 0066H Prohibit RMW 0 Input 1 Output PR3F PR2F PR1F PR0F W 0 0 0 0 PRFC PORTR function register 0067H Prohibit RMW 0 Port 1 SPCLK 0 Port 1 SPCS 0 Port 1 SPDO 0 Port 1 SPDI PT7C PT6C PT5C PT4C P...

Page 592: ...0 0 PVFC2 PORTV function register 2 00A9H Prohibit RMW 0 CMOS 1 Open drain 0 CMOS 1 Open drain PX5C W 0 PXCR PORT X control register 00B2H Prohibit RMW 0 Input 1 Output PX5F PX4F W 0 0 PXFC PORT X function register 00B3H Prohibit RMW 0 Port 1 X1USB input at PX5C 0 X1D4 output at PX5C 1 PX5 1 0 Port 1 CLKOUT at PX4 0 PX5F2 PX4F2 W 0 0 PXFC2 PORT X function register 2 00B1H Prohibit RMW X1D4 output ...

Page 593: ...D P62D P61D P60D R W 1 1 1 1 1 1 1 1 P6DR PORT6 drive register 0086H Input Output buffer drive register for standby mode P76D P75D P74D P73D P72D P71D P70D R W 1 1 1 1 1 1 1 P7DR PORT7 drive register 0087H Input Output buffer drive register for standby mode P87D P86D P83D P82D P81D P80D R W R W 1 1 1 1 1 1 P8DR PORT8 drive register 0088H Input Output buffer drive register for standby mode P97D P96...

Page 594: ...2D PM1D R W R W 1 1 1 PMDR PORTM drive register 0096H Input Output buffer drive register for standby mode PN7D PN6D PN5D PN4D PN3D PN2D PN1D PN0D R W 1 1 1 1 1 1 1 1 PNDR PORTN drive register 0097H Input Output buffer drive register for standby mode PP6D PP5D PP4D PP3D R W 1 1 1 1 PPDR PORTP drive register 0098H Input Output buffer drive register for standby mode PR3D PR2D PR1D PR0D R W 1 1 1 1 PR...

Page 595: ... enable 00D5H 0 0 0 0 0 0 0 0 INTTA5 TMRA5 INTTA4 TMRA4 ITA5C ITA5M2 ITA5M1 ITA5M0 ITA4C ITA4M2 ITA4M1 ITA4M0 R R W R R W INTETA45 INTTA4 INTTA5 enable 00D6H 0 0 0 0 0 0 0 0 INTTA7 TMRA7 INTTA6 TMRA6 ITA7C ITA7M2 ITA7M1 ITA7M0 ITA6C ITA6M2 ITA6M1 ITA6M0 R R W R R W INTETA67 INTTA6 INTTA7 enable 00D7H 0 0 0 0 0 0 0 0 INTTB01 TMRB0 INTTB00 TMRB0 ITB01C ITB01M2 ITB01M1 ITB01M0 ITB00C ITB00M2 ITB00M1 ...

Page 596: ... INTRTC IRC IRM2 IRM1 IRM0 R R W INTERTC INTRTC enable 00E8H Always write 0 0 0 0 0 INTKEY IKC IKM2 IKM1 IKM0 R R W INTEKEY INTKEY enable 00E9H Always write 0 0 0 0 0 INTI2S0 II2S0C II2S0M2 II2S0M1 II2S0M0 R R W INTEI2S0 INTI2S0 enable 00EBH Always write 0 0 0 0 0 INTRSC INTRDY IRSCC IRSCM2 IRSCM1 IRSCM0 IRDYC IRDYM2 IRDYM1 IRDYM0 R R W R R W INTENDFC INTRSC INTRDY enable 00ECH 0 0 0 0 0 0 0 0 INT...

Page 597: ...ITC7M2 ITC7M1 ITC7M0 ITC6C ITC6M2 ITC6M1 ITC6M0 R R W R R W INTETC67 INTTC6 INTTC7 enable 00F4H 0 0 0 0 0 0 0 0 IR1LE IR0LE W W 0 0 1 1 SIMC SIO interrupt mode control 00F5H Prohibit RMW Always write 0 Always write 0 0 INTRX1 edge mode 1 INTRX1 level mode 0 INTRX0 edge mode 1 INTRX0 level mode I5EDGE I4EDGE I3EDGE I2EDGE I1EDGE I0EDGE I0LE NMIREE W R W R W 0 0 0 0 0 0 0 0 IIMC0 Interrupt input mod...

Page 598: ...MA4 start vector DMA5V5 DMA5V4 DMA5V3 DMA5V2 DMA5V1 DMA5V0 R W 0 0 0 0 0 0 DMA5V DMA5 start vector 0105H DMA5 start vector DMA6V5 DMA6V4 DMA6V3 DMA6V2 DMA6V1 DMA6V0 R W 0 0 0 0 0 0 DMA6V DMA6 start vector 0106H DMA6 start vector DMA7V5 DMA7V4 DMA7V3 DMA7V2 DMA7V1 DMA7V0 R W 0 0 0 0 0 0 DMA7V DMA7 start vector 0107H DMA7 start vector DBST7 DBST6 DBST5 DBST4 DBST3 DBST2 DBST1 DBST0 R W 0 0 0 0 0 0 0...

Page 599: ... 4 waits 1001 6 waits 1011 8 waits 1101 10 waits 1111 16 waits 0010 1 waits 0110 3 waits 1000 5 waits 1010 7 waits 1100 9 waits 1110 12 waits 0100 20 waits 0011 6 states WAIT pin input mode 0011 6 states WAIT pin input mode B1CSL BLOCK1 CS WAIT control register low 0144H Others Reserved Others Reserved B1E B1REC B1OM1 B1OM0 B1BUS1 B1BUS0 R W R W 0 0 0 0 0 0 B1CSH BLOCK1 CS WAIT control register hi...

Page 600: ...sable 1 Enable Dummy cycle 0 No insert 1 Insert 00 ROM SRAM 01 Reserved 10 Reserved 11 Reserved Data bus width 00 8 bits 01 16 bits 10 Reserved 11 Don t set BEXWW3 BEXWW2 BEXWW1 BEXWW0 BEXWR3 BEXWR2 BEXWR1 BEXWR0 R W 0 0 1 0 0 0 1 0 Write waits Read waits 0001 0 waits 0101 2 waits 0111 4 waits 1001 6 waits 1011 8 waits 1101 10 waits 1111 16 waits 0010 1 waits 0110 3 waits 1000 5 waits 1010 7 waits...

Page 601: ...isable M1S23 M1S22 M1S21 M1S20 M1S19 M1S18 M1S17 M1S16 R W 1 1 1 1 1 1 1 1 MSAR1 Memory start address register 1 0147H Set start address A23 to A16 M2V22 M2V21 M2V20 M2V19 M2V18 M2V17 M2V16 M2V15 R W 1 1 1 1 1 1 1 1 MAMR2 Memory address mask register 2 014AH 0 Compare enable 1 Compare disable M2S23 M2S22 M2S21 M2S20 M2S19 M2S18 M2S17 M2S16 R W 1 1 1 1 1 1 1 1 MSAR2 Memory start address register 2 ...

Page 602: ...S 10 2 5 1 fSYS 11 3 5 1 fSYS B1TCRS1 B1TCRS0 B1TCRH1 B1TCRH0 B0TCRS1 B0TCRS0 B0TCRH1 B0TCRH0 R W 0 0 0 0 0 0 0 0 RDTMGCR0 Adjust for Timing of control signal 016AH Select delay time TCRS 00 0 5 1 fSYS 01 1 5 1 fSYS 10 2 5 1 fSYS 11 3 5 1 fSYS Select delay time TCRH 00 0 1 fSYS 01 1 1 fSYS 10 2 1 fSYS 11 3 1 fSYS Select delay time TCRS 00 0 5 1 fSYS 01 1 5 1 fSYS 10 2 5 1 fSYS 11 3 5 1 fSYS Select...

Page 603: ...trol of Port 96 97 0 Enable 1 Disable Detection condition 0 no touch 1 touch INT4 interrupt control 0 Disable 1 Enable SPY 0 OFF 1 ON SPX 0 OFF 1 ON SMY 0 OFF 1 ON SMX 0 OFF 1 ON DBC7 DB1024 DB256 DB64 DB8 DB4 DB2 DB1 R W 0 0 0 0 0 0 0 0 1024 256 64 8 4 2 1 TSICR1 TSI control register1 01F1H 0 Disable 1 Enable De bounce time is set by N 64 16 fSYS formula N is sum of number which is set to 1 in bi...

Page 604: ... CLK 111 8 CLK SSAE SRS2 SRS1 SRS0 SRC R W R W 0 1 0 0 0 0 SDRCR SDRAM refresh control register 0252H Always write 0 Self Refresh auto exit function 0 Disable 1 Enable Refresh interval 000 47 states 100 468 states 001 78 states 101 624 states 010 156 states 110 936 states 011 312 states 111 1248 states Auto Refresh 0 Disable 1 Enable SCMM2 SCMM1 SCMM0 R W 0 0 0 SDCMM SDRAM command register 0253H C...

Page 605: ... Descriptor RAM383 Descriptor RAM 383 register 067FH Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined EP0_DATA7 EP0_DATA6 EP0_DATA5 EP0_DATA4 EP0_DATA3 EP0_DATA2 EP0_DATA1 EP0_DATA0 R W Endpoint0 Endpoint 0 register 0780H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined EP1_DATA7 EP1_DATA6 EP1_DATA5 EP1_DATA4 EP1_DATA3 EP1_DATA2 EP1_DAT...

Page 606: ...e register Low A 0799H 1 0 0 0 1 0 0 0 PKT_ACTIVE DATASIZE6 DATASIZE5 DATASIZE4 DATASIZE3 DATASIZE2 DATASIZE1 DATASIZE0 R EP2_SIZE_L_A Endpoint 2 size register Low A 079AH 1 0 0 0 1 0 0 0 PKT_ACTIVE DATASIZE6 DATASIZE5 DATASIZE4 DATASIZE3 DATASIZE2 DATASIZE1 DATASIZE0 R EP3_SIZE_L_A Endpoint 3 size register Low A 079BH 1 0 0 0 1 0 0 0 PKT_ACTIVE DATASIZE6 DATASIZE5 DATASIZE4 DATASIZE3 DATASIZE2 DA...

Page 607: ...ister 07C1H 0 0 0 0 0 0 0 0 VALUE_L7 VALUE_L6 VALUE_L5 VALUE_L4 VALUE_L3 VALUE_L2 VALUE_L1 VALUE_L0 R wValue_L wValue register Low 07C2H 0 0 0 0 0 0 0 0 VALUE_H7 VALUE_H6 VALUE_H5 VALUE_H4 VALUE_H3 VALUE_H2 VALUE_H1 VALUE_H0 R wValue_H wValue register High 07C3H 0 0 0 0 0 0 0 0 INDEX_L7 INDEX_L6 INDEX_L5 INDEX_L4 INDEX_L3 INDEX_L2 INDEX_L1 INDEX_L0 R wIndex_L wIndex register Low 07C4H 0 0 0 0 0 0 ...

Page 608: ..._DSET_A EP5_DSET_B EP5_DSET_A EP4_DSET_B EP4_DSET_A R DATASET2 DATASET 2 register 07CDH 0 0 0 0 0 0 0 0 Configured Addressed Default R W R USB_STATE USB state register 07CEH 0 0 1 EP7_EOPB EP6_EOPB EP5_EOPB EP4_EOPB EP3_EOPB EP2_EOPB EP1_EOPB EP0_EOPB W EOP EOP register 07CFH 1 1 1 1 1 1 1 1 EP 2 EP 1 EP 0 Command 3 Command 2 Command 1 Command 0 W COMMAND Command register 07D0H 0 0 0 0 0 0 0 EP3_S...

Page 609: ... INT_CLKON R W 0 0 0 0 0 0 USBINTFR1 USB interrupt flag register 1 07F0H Prohibit RMW When read 0 Not generate interrupt 1 Generate interrupt When write 0 Clear flag 1 EP1_FULL_A EP1_Empty_A EP1_FULL_B EP1_Empty_B EP2_FULL_A EP2_Empty_A EP2_FULL_B EP2_Empty_B R W 0 0 0 0 0 0 0 0 USBINTFR2 USB interrupt flag register 2 07F1H Prohibit RMW When read 0 Not generate interrupt 1 Generate interrupt When ...

Page 610: ..._EA EP2_MSK_FB EP2_MSK_EB R W 1 1 1 1 1 1 1 1 USBINTMR2 USB interrupt mask register 2 07F5H 0 Be not masked 1 Be masked EP3_MSK_FA EP3_MSK_EA R W 1 1 USBINTMR3 USB interrupt mask register 3 07F6H 0 Be not masked 1 Be masked MSK_SETUP MSK_EP0 MSK_STAS MSK_STASN MSK_EP1N MSK_EP2N MSK_EP3N R W 1 1 1 1 1 1 1 USBINTMR4 USB interrupt mask register 4 07F7H 0 Be not masked 1 Be masked TRNS_USE WAKEUP SPEE...

Page 611: ...MOD TXE FDPXE RXMOD RXE R W 0 1 0 0 0 0 0 0 0822H communica tion control 0 disable 1 enable SPCS pin 0 output 0 1 output 1 Data length 0 8bit 1 16bit Transmit mode 0 UNIT 1 Sequential Transmit control 0 disable 1 enable Alignment in Full duplex 0 disable 1 enable Receive Mode 0 UNIT 1 Sequential Receive control 0 disable 1 enable CRC16_7_B CRCRX_TX_B CRCRESET_B R W 0 0 0 SPICT SPI Control register...

Page 612: ...1H Transmit data register 15 8 TXD7 TXD6 TXD5 TXD4 TXD3 TXD2 TXD1 TXD0 R W 0 0 0 0 0 0 0 0 0832H Transmit data register 7 0 TXD15 TXD14 TXD13 TXD12 TXD11 TXD10 TXD9 TXD8 R W 0 0 0 0 0 0 0 0 SPITD1 SPI transmission data1 register 0833H Transmit data register 15 8 RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0 R 0 0 0 0 0 0 0 0 0834H Receive data register 7 0 RXD15 RXD14 RXD13 RXD12 RXD11 RXD10 RXD9 RXD8 R...

Page 613: ...0 0882H Specify the bank number for the LOCAL Y area Since bank 3 is overlapping with the COMMON area this filed must not be specified as 3 LYE R W 0 LOCALPY LOCALY register for program 0883H Bank for LOCAL Y 0 Disable 1 Enable Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 R W 0 0 0 0 0 0 0 0 0884H Specify the bank number for the LOCAL Z area Since bank 3 is overlapping with the COMMON area this filed must not be speci...

Page 614: ...0 0 0892H Specify the bank number for the LOCAL Y area Since bank 3 is overlapping with the COMMON area this filed must not be specified as 3 LYE R W 0 LOCALRY LOCALY register for read 0893H Bank for LOCAL Y 0 Disable 1 Enable Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 R W 0 0 0 0 0 0 0 0 0894H Specify the bank number for the LOCAL Z area Since bank 3 is overlapping with the COMMON area this filed must not be specif...

Page 615: ... 0 089AH Specify the bank number for the LOCAL Y area Since bank 3 is overlapping with the COMMON area this filed must not be specified as 3 LYE R W 0 LOCALWY LOCALY register for write 089BH Bank for LOCAL Y 0 Disable 1 Enable Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 R W 0 0 0 0 0 0 0 0 089CH Specify the bank number for the LOCAL Z area Since bank 3 is overlapping with the COMMON area this filed must not be specif...

Page 616: ...08A2H Specify the bank number for the LOCAL Y area Since bank 3 is overlapping with the COMMON area this filed must not be specified as 3 LYE R W 0 LOCALESY LOCALY register for DMA source 08A3H Bank for LOCAL Y 0 Disable 1 Enable Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 R W 0 0 0 0 0 0 0 0 08A4H Specify the bank number for the LOCAL Z area Since bank 3 is overlapping with the COMMON area this filed must not be spe...

Page 617: ...AAH Specify the bank number for the LOCAL Y area Since bank 3 is overlapping with the COMMON area this filed must not be specified as 3 LYE R W 0 LOCALEDY LOCALY register for DMA destination 08ABH Bank for LOCAL Y 0 Disable 1 Enable Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 R W 0 0 0 0 0 0 0 0 08ACH Specify the bank number for the LOCAL Z area Since bank 3 is overlapping with the COMMON area this filed must not be ...

Page 618: ...08B2H Specify the bank number for the LOCAL Y area Since bank 3 is overlapping with the COMMON area this filed must not be specified as 3 LYE R W 0 LOCALOSY LOCALY register for DMA source 08B3H Bank for LOCAL Y 0 Disable 1 Enable Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 R W 0 0 0 0 0 0 0 0 08B4H Specify the bank number for the LOCAL Z area Since bank 3 is overlapping with the COMMON area this filed must not be spe...

Page 619: ...BAH Specify the bank number for the LOCAL Y area Since bank 3 is overlapping with the COMMON area this filed must not be specified as 3 LYE R W 0 LOCALODY LOCALY register for DMA destination 08BBH BANK for LOCAL Y 0 Disable 1 Enable Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 R W 0 0 0 0 0 0 0 0 08BCH Specify the bank number for the LOCAL Z area Since bank 3 is overlapping with the COMMON area this filed must not be ...

Page 620: ...ror calculation start 0 1 Start Always read as 0 Reed Solomon ECC generator write control 0 Disable 1 Enable INTERDY INTRSC BUSW ECCS SYSCKE R W R W R W R W R W 0 0 0 0 0 08C2H Ready interrupt 0 Disable 1 Enable Reed Solomon calculation end interrupt 0 Disable 1 Enable Data bus width 0 8 bit 1 16 bit ECC calculation 0 Hamming 1 Reed Solomon Clock control 0 Disable 1 Enable STATE3 STATE2 STATE1 STA...

Page 621: ...NAND Flash ECC Register 15 8 ECCD7 ECCD6 ECCD5 ECCD4 ECCD3 ECCD2 ECCD1 ECCD0 R 0 0 0 0 0 0 0 0 08CAH NAND Flash ECC Register 7 0 ECCD15 ECCD14 ECCD13 ECCD12 ECCD11 ECCD10 ECCD9 ECCD8 R 0 0 0 0 0 0 0 0 NDECCRD3 NANDF Code ECC Register3 08CBH NAND Flash ECC Register 15 8 ECCD7 ECCD6 ECCD5 ECCD4 ECCD3 ECCD2 ECCD1 ECCD0 R 0 0 0 0 0 0 0 0 08CCH NAND Flash ECC Register 7 0 ECCD15 ECCD14 ECCD13 ECCD12 EC...

Page 622: ...sh Reed Solomon Calculation Result Address Register 7 0 RS1A9 RS1A8 R 0 0 NDRSCA1 NANDF read solomon Result address Register1 08D5H NAND Flash Reed Solomon Calculation Result Address Register 9 8 RS1D7 RS1D6 RS1D5 RS1D4 RS1D3 RS1D2 RS1D1 RS1D0 R 0 0 0 0 0 0 0 0 NDRSCD1 NANDF read solomon Result data Register1 08D6H NAND Flash Reed Solomon Calculation Result Data Register 7 0 RS2A7 RS2A6 RS2A5 RS2A...

Page 623: ...Flash Reed Solomon Calculation Result Data Register 7 0 D7 D6 D5 D4 D3 D2 D1 D0 R W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 1FF0H NAND Flash Data Register 7 0 D15 D14 D13 D12 D11 D10 D9 D8 R W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined NDFDTR0 NANDF Data Register0 1FF1H NAND Flash Data Register 15 8 D7 D6 D5 D4 D3 D2 D1 D...

Page 624: ...ddress Register0 0906H Destination address for DMA0 23 16 D0CA7 D0CA6 D0CA5 D0CA4 D0CA3 D0CA2 D0CA1 D0CA0 R W 0 0 0 0 0 0 0 0 0908H Transfer count A 7 0 for DMA0 D0CA15 D0CA14 D0CA13 D0CA12 D0CA11 D0CA10 D0CA9 D0CA8 R W 0 0 0 0 0 0 0 0 HDMACA0 DMA Transfer count number A Register0 0909H Transfer count A 15 8 for DMA0 D0CB7 D0CB6 D0CB5 D0CB4 D0CB3 D0CB2 D0CB1 D0CB0 R W 0 0 0 0 0 0 0 0 090AH Transfe...

Page 625: ...r1 0916H Set destination address for DMA1 23 16 D1CA7 D1CA6 D1CA5 D1CA4 D1CA3 D1CA2 D1CA1 D1CA0 R W 0 0 0 0 0 0 0 0 0918H Set transfer count number A for DMA1 7 0 D1CA15 D1CA14 D1CA13 D1CA12 D1CA11 D1CA10 D1CA9 D1CA8 R W 0 0 0 0 0 0 0 0 HDMACA1 DMA Transfer count number A Register1 0919H Set transfer count number A for DMA1 15 8 D1CB7 D1CB6 D1CB5 D1CB4 D1CB3 D1CB2 D1CB1 D1CB0 R W 0 0 0 0 0 0 0 0 0...

Page 626: ...ddress Register2 0926H Destination address for DMA2 23 16 D2CA7 D2CA6 D2CA5 D2CA4 D2CA3 D2CA2 D2CA1 D2CA0 R W 0 0 0 0 0 0 0 0 0928H Transfer count A 7 0 for DMA2 D2CA15 D2CA14 D2CA13 D2CA12 D2CA11 D2CA10 D2CA9 D2CA8 R W 0 0 0 0 0 0 0 0 HDMACA2 DMA Transfer count number A Register2 0929H Transfer count A 15 8 for DMA2 D2CB7 D2CB6 D2CB5 D2CB4 D2CB3 D2CB2 D2CB1 D2CB0 R W 0 0 0 0 0 0 0 0 092AH Transfe...

Page 627: ...nation address Register3 0936H Set destination address for DMA3 23 16 D3CA7 D3CA6 D3CA5 D3CA4 D3CA3 D3CA2 D3CA1 D3CA0 R W 0 0 0 0 0 0 0 0 0938H Transfer count A 7 0 for DMA3 D3CA15 D3CA14 D3CA13 D3CA12 D3CA11 D3CA10 D3CA9 D3CA8 R W 0 0 0 0 0 0 0 0 HDMACA3 DMA Transfer count number A Register3 0939H Transfer count A 15 8 for DMA3 D3CB7 D3CB6 D3CB5 D3CB4 D3CB3 D3CB2 D3CB1 D3CB0 R W 0 0 0 0 0 0 0 0 0...

Page 628: ...dress Register4 0946H Destination address for DMA4 23 16 D4CA7 D4CA6 D4CA5 D4CA4 D4CA3 D4CA2 D4CA1 D4CA0 R W 0 0 0 0 0 0 0 0 0948H Transfer count A 15 8 for DMA4 D4CA15 D4CA14 D4CA13 D4CA12 D4CA11 D4CA10 D4CA9 D4CA8 R W 0 0 0 0 0 0 0 0 HDMACA4 DMA Transfer count number A Register4 0949H Transfer count A 15 8 for DMA4 D4CB7 D4CB6 D4CB5 D4CB4 D4CB3 D4CB2 D4CB1 D4CB0 R W 0 0 0 0 0 0 0 0 094AH Transfe...

Page 629: ...dress Register5 0956H Destination address for DMA5 23 16 D5CA7 D5CA6 D5CA5 D5CA4 D5CA3 D5CA2 D54CA1 D5CA0 R W 0 0 0 0 0 0 0 0 0958H Transfer count A 7 0 for DMA5 D5CA15 D5CA14 D5CA13 D5CA12 D5CA11 D5CA10 D5CA9 D5CA8 R W 0 0 0 0 0 0 0 0 HDMACA5 DMA Transfer count number A Register5 0959H Transfer count A 15 8 for DMA5 D5CB7 D5CB6 D5CB5 D5CB4 D5CB3 D5CB2 D5CB1 D5CB0 R W 0 0 0 0 0 0 0 0 095AH Transfe...

Page 630: ...able Register 097EH DMA channel operation 0 Disable 1 Enable DMATE DMATR6 DMATR5 DMATR4 DMATR3 DMATR2 DMATR1 DMATR0 R W 0 0 0 0 0 0 0 0 HDMATR DMA timer Register 097FH Timer operation 0 Disable 1 Enable Maximum bus occupancy time setting The value to be set in DMATR6 0 should be obtained by Maximum bus occupancy time 256 fSYS 00H cannot be set ...

Page 631: ... 214 inputted frequency 11 216 inputted frequency HALT mode 00 Reserved 01 STOP mode 10 IDLE1 mode 11 IDLE2 mode PROTECT EXTIN DRVOSCH DRVOSCL R R W R W R W R W 0 0 0 1 1 EMCCR0 EMC control register0 10E3H Protect flag 0 OFF 1 ON Always write 0 1 External clock fc oscillator drive ability 1 NORMAL 0 WEAK fs oscillator drive ability 1 NORMAL 0 WEAK EMCCR1 EMC control register1 10E4H EMCCR2 EMC cont...

Page 632: ... 00 Invert TA1FF 01 Set TA1FF 10 Clear TA1FF 11 Don t care TA1FF control for inversion 0 Disable 1 Enable TA1FF inversion select 0 TMRA0 1 TMRA1 TA2RDE I2TA23 TA23PRUN TA3RUN TA2RUN R W R W 0 0 0 0 0 TMRA23 prescaler Up counter UC3 Up counter UC2 TA23RUN TMRA23 RUN register 1108H Double buffer 0 Disable 1 Enable IDLE2 0 Stop 1 Operate 0 Stop and clear 1 Run Count up W TA2REG 8 bit timer register 2...

Page 633: ...φT1 10 φT4 11 φT16 TA6RDE I2TA67 TA67PRUN TA7RUN TA6RUN R W R W 0 0 0 0 0 TMRA67 prescaler Up counter UC7 Up counter UC6 TA67RUN TMRA67 RUN register 1118H Double buffer 0 Disable 1 Enable IDLE2 0 Stop 1 Operate 0 Stop and clear 1 Run Count up W TA6REG 8 bit timer register 2 111AH Prohibit RMW 0 W TA7REG 8 bit timer register 3 111BH Prohibit RMW 0 TA67M1 TA67M0 PWM61 PWM60 TA7CLK1 TA7CLK0 TA6CLK1 T...

Page 634: ...ble TMRB1 source clock 00 TB0IN0 input 01 φT1 10 φT4 11 φT16 TB0CT1 TB0C0T1 TB0E1T1 TB0E0T1 TB0FF0C1 TB0FF0C0 W R W W 1 1 0 0 0 0 1 1 TB1FF0 inversion trigger 0 Disable trigger 1 Enable trigger TB0FFCR TMRB0 Flip Flop control register 1183H Prohibit RMW Always write 11 Always read as 11 When capture UC10 to TB0CP1H L When capture UC10 to TB0CP0H L When UC10 matches with TB0RG1H L When UC10 matches...

Page 635: ...ing 00 Disable INT7 occurs at rising edge 01 TB1IN0 INT7 occurs at rising edge 10 TB1IN0 TB1IN0 INT7 occurs at falling edge 11 TA3OUT TA3OUT INT7 occurs at rising edge Control Up counter 0 Clear Disable 1 Clear Enable TMRB1 source clock 00 TB1IN0 input 01 φT1 10 φT4 11 φT16 W TB1RG0L 16 bit timer register 0 low 1198H Prohibit RMW 0 W TB1RG0H 16 bit timer register 0 high 1199H Prohibit RMW 0 W TB1R...

Page 636: ...I O interface Mode 01 7 bit UART Mode 10 8 bit UART Mode 11 9 bit UART Mode 00 TA0TRG 01 Baud rate generator 10 Internal clock fIO 11 External clock SCLK0 input BR0ADDE BR0CK1 BR0CK0 BR0S3 BR0S2 BR0S1 BR0S0 R W 0 0 0 0 0 0 0 0 BR0CR Serial channel 0 baud rate control register 1203H Always write 0 16 K 16 division 0 Disable 1 Enable 00 φT0 01 φT2 10 φT8 11 φT32 Divided frequency N setting 0 F BR0K3...

Page 637: ...I O interface Mode 01 7 bit UART Mode 10 8 bit UART Mode 11 9 bit UART Mode 00 TA0TRG 01 Baud rate generator 10 Internal clock fIO 11 External clock SCLK1 input BR1ADDE BR1CK1 BR1CK0 BR1S3 BR1S2 BR1S1 BR1S0 R W 0 0 0 0 0 0 0 0 BR1CR Serial channel 1 baud rate control register 120CH Always write 0 16 K 16 division 0 Disable 1 Enable 00 φT0 01 φT2 10 φT8 11 φT32 Divided frequency N setting 0 F BR1K3...

Page 638: ...s monitor 0 Free 1 Busy INTSBI request monitor 0 Request 1 Cancel Arbitration lost detection monitor 0 1 Detected Slave Address match detection monitor 0 Undetected 1 Detected General call detection monitor 0 Undetected 1 Detected Last receive bit monitor 0 0 1 1 SBICR2 When write Serial bus interface control register 2 1243H Prohibit RMW Master Slave status monitor 0 Slave 1 Master Transmitter Re...

Page 639: ...27 ADR26 ADR25 ADR24 ADR23 ADR22 R 0 0 0 0 0 0 0 0 ADREG2H AD conversion result register 2 high 12A5H Store Upper 8 bits of an AN2 conversion result ADR31 ADR30 OVR3 ADR3RF R R 0 0 0 0 ADREG3L AD conversion result register 3 low 12A6H Store Lower 2 bits of AN3 AD conversion result Overrun flag 0 No generate 1 Generate AD conversion result store flag 1 Stored ADR39 ADR38 ADR37 ADR36 ADR35 ADR34 ADR...

Page 640: ... Store Upper 8 bits of an AD conversion result compare criterion ADR21 ADR20 R W 0 0 ADCM1REGL AD Conversion Result Compare Criterion Register 1 Low 12B6H Store Lower 2 bits of an AD conversion result compare criterion ADR29 ADR28 ADR27 ADR26 ADR25 ADR24 ADR23 ADR22 R W 0 0 0 0 0 0 0 0 ADCM1REGH AD Conversion Result Compare Criterion Register 1 High 12B7H Store Upper 8 bits of an AD conversion res...

Page 641: ... 0 0 0 0 0 ADMOD3 AD mode control register 3 12BBH Always write 0 High priority analog input channel select Always write 0 CMEN1 CMEN0 CMP1C CMP0C IRQEN1 IRQEN0 CMPINT1 CMPINT0 R W 0 0 0 0 0 0 0 0 ADMOD4 AD mode control register 4 12BCH AD Monitor function1 0 Disable 1 Enable AD Monitor function0 0 Disable 1 Enable Generation condition of AD monitor function interrupt 1 0 less than 1 Greater than ...

Page 642: ...CR R W R W 1 0 0 0 0 0 WDMOD WDT mode register 1300H WDT control 1 Enable Select detecting time 00 2 15 fIO 01 2 17 fIO 10 2 19 fIO 11 2 21 fIO IDLE2 0 Stop 1 Operate 1 Internally connects WDT out to the reset pin Always write 0 W WDCR WDT control register 1301H Prohibit RMW B1H WDT disable code 4E WDT clear code ...

Page 643: ...2 MO1 MO0 R W 1325H Undefined PAGE0 0 is read 10 month 8 month 4 month 2 month 1 month MONTHR Month register PAGE1 0 is read 0 Indicator for 12 hours 1 Indicator for 24 hours YE7 YE6 YE5 YE4 YE3 YE2 YE1 YE0 R W 1326H Undefined PAGE0 80 years 40 years 20 years 10 years 8 years 4 years 2 years 1 year YEARR Year register PAGE1 0 is read Leap year setting 00 Leap year 01 One year after 10 Two years af...

Page 644: ...quency invert 1 Invert Always write 0 Output frequency 0 Alarm 1 Melody ML7 ML6 ML5 ML4 ML3 ML2 ML1 ML0 R W 0 0 0 0 0 0 0 0 MELFL Melody frequency L register 1332H Melody frequency set Low 8bit MELON ML11 ML10 ML9 ML8 R W R W 0 0 0 0 0 MELFH Melody frequency H register 1333H Melody counter control 0 Stop and clear 1 Start Melody frequency set Upper 4 bits IALM4E IALM3E IALM2E IALM1E IALM0E R W 0 0...

Page 645: ...p 1 Start Counter control 0 Clear 1 Start Transmi ssion start BIT 0 MSB 1 LSB Bit length 0 8 bits 1 16 bits 00 I2 S 01 Left 10 Right 11 Reserved System clock 0 Disable 1 Enable CLKS0 FSEL0 TEMP0 WLVL0 EDGE0 CLKE0 R W R W R R W 0 0 1 0 0 0 I2S0CTL I 2 S Control Register0 1809H Source clock 0 fSYS 1 fPLL Stereo monaural 0 Stereo 1 Monaural Condition of transmission FIFO 0 data 1 None data WS level 0...

Page 646: ...ndefined MACMB_LH Data register Multiplier B LH 1BE5H Multiplier B data register 15 8 MB23 MB22 MB21 MB20 MB19 MB18 MB17 MB16 R W Undefined MACMB_HL Data register Multiplier B HL 1BE6H Multiplier B data register 23 16 MB31 MB30 MB29 MB28 MB27 MB26 MB25 MB24 R W Undefined MACMB_HH Data register Multiplier B HH 1BE7H Multiplier B data register 31 24 OR7 OR6 OR5 OR4 OR3 OR2 OR1 OR0 R W Undefined MACO...

Page 647: ...e HHL 1BEEH Multiply and Accumulate data register 55 48 OR63 OR62 OR61 OR60 OR59 OR58 OR57 OR56 R W Undefined MACOR_HHH Data register Multiply and Accumulate HHH 1BEFH Multiply and Accumulate data register 63 56 MOVF MOPST MSTTG2 MSTTG1 MSTTG0 MSGMD MOPMD1 MOPMD0 R W W R W R W R W 0 0 0 0 0 0 0 0 MACCR MAC Control Register 1BFCH Over flow flag 0 no over flow 1 generate over flow Start calculation ...

Page 648: ...s on the TLCS 900 Exchange instruction EX mem R Arithmetic operations ADD mem R ADC mem R SUB mem R SBC mem R INC 3 mem DEC 3 mem Logic operations AND mem R OR mem R XOR mem R Bit manipulation operations STCF 3 A mem RES 3 mem SET 3 mem CHG 3 mem TSET 3 mem Rotate and shift operations RLC mem RRC mem RL mem RR mem SLA mem SRA mem SLL mem SRL mem RLD mem RRD mem 3 fOSCH fc fSYS fIO and one state Th...

Page 649: ...4 Warm up timer The warm up timer operates when STOP mode is released even if the system is using an external oscillator As a result a time equivalent to the warm up time elapses between input of the release request and output of the system clock 5 Watchdog timer The watchdog timer starts operation immediately after a reset is released Disable the watchdog timer when it is not to be used 6 AD conv...

Page 650: ...TMP92CF30 2009 06 12 92CF30 648 7 Package Dimensions LQFP176 P 2020 0 40F TOP VIEW BOTTOM VIEW Detail view of A 25 1 A ...

Page 651: ...r facilities equipment used in the aerospace industry medical equipment equipment used for automobiles trains ships and other transportation traffic signaling equipment equipment used to control combustions or explosions safety devices elevators and escalators devices related to electric power and equipment used in finance related fields Do not use Product for Unintended Use unless specifically pe...

Page 652: ...TMP92CF30 2009 06 12 92CF30 650 ...

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