TMP92CF30
2009-06-12
92CF30-353
3.16.3 UDC CORE
3.16.3.1 SFRs
The UDC CORE has the following SFRs to control the UDC and USB transceiver.
a)
FIFO
Endpoint 0 to 3 FIFO register
b)
Device request
bmRequestType register
bRequest
register
wValue_L register
wValue_H
register
wIndex_L register
wIndex_H
register
wLength_L register
wLength_H
register
c)
Status
Current_Config register
USB_STATE
register
StandardRequest register
Request
register
EPx_STATUS register
d)
Setup
EPx_BCS register
EPx_SINGLE
register
Standard Request Mode
register
Request Mode
register
Descriptor RAM
register
PortStatus
register
e)
Control
EPx_MODE register EOP
register
COMMAND register
INT_
Control
register
Setup Received
register
USBREADY
register
f)
Others
ADDRESS register
DATASET
register
EPx_SIZE_L_A register
EPx_SIZE_H_A register
EPx_SIZE_L_B register
EPx_SIZE_H_B register
FRAME_L register
FRAME_H
register
USBBUFF TEST
register
Summary of Contents for TLCS-900/H1 Series
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