Toshiba ESTUDIO170F, Service Manual

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e-STUDIO170F Circuit Description January 2005 © TOSHIBA TEC
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148 DSCCK O DSC operation clock (16 MHz)
Operation clock for the DSC.
150 OBACKX O CODEC bus acknowledge 2 signal (Low-active)
Indicates release of the bus to the CODEC.
151 ODREQX I CODEC DMA request 2 signal (Low-active)
The CODEC makes a request for DMA transfer.
152 ODACKX O CODEC DMA acknowledge 2 signal (Low-active)
Indicates the start of DMA transfer to the CODEC.
153 PM22CSX O CODEC chip select signal (Low-active)
Selects the CODEC.
154 INTPMX I CODEC interrupt signal
The CODEC requests the ASIC (Engine controller) to
perform interruption.
155 IBACKX O CODEC bus acknowledge 1 signal (Low-active)
Indicates release of the bus to the CODEC.
156 IDREQX I CODEC DMA request 1 signal (Low-active)
The CODEC makes a request for DMA transfer.
157 IDACKX O CODEC DMA acknowledge 1 signal (Low-active)
Indicates the start of DMA transfer to the CODEC.
159 PM22CK O CODEC operation clock (32 MHz)
Operation clock for the CODEC.
162-169 PMID[0]-[7] O CODEC output data bus
Bus for data output to CODEC.
171-178 PMOD[0]-[7] I CODEC input data bus
Bus for data input from CODEC.
182 X32M I System clock input (32 MHz)
183-190, 192-199 SDD[0]-[15] I/O SDRAM data bus
Data bus for the SDRAM (IC1).
202 SDDQMH O SDRAM upper data DQM signal (Low-active)
Masks the SDRAM upper data.
203 SDCLK O SDRAM operation clock (64 MHz)
204 SDCKIN I SDRAM operation clock detect signal
205 SDCKE O SDRAM clock enable signal (High-active)
Enables the SDCLK signal inputted in the SDRAM.
206-209, 211-213,
223-227
SDA[0]-[11] O SDRAM address bus
Address bus for the SDRAM.
214 SDDQML O SDRAM lower data DQM signal (Low-active)
Masks the SDRAM lower data.
215 SDWEX O SDRAM write signal (H: Read, L: Write)
Writes data to the SDRAM or reads data from the
SDRAM.
216 SDCASX O SDRAM CAS signal (Low-active)
CAS signal for the SDRAM.
217 SDRASX O SDRAM RAS signal (Low-active)
RAS signal for the SDRAM.
218 SDCSX O SDRAM chip select signal (Low-active)
Selects the SDRAM.
219, 222 SDBA[0], [1] O SDRAM bank address bus
Address bus for the bank memory function of the
SDRAM.
230 PTCCK1 I 16 dots/mm clock (Facsimile-related clock)
Reference clock for printing in 16 dots/mm (406 dpi).
231 PTCCK2 I 300/600 dpi clock (Printer-related clock)
Reference clock for printing in 300/600 dpi.
232 IDTCLK - Not used
Pin No. Signal name I/O Function