Performance Considerations
7-24
7.5
Performance Considerations
The interaction of the ’C62x/C67x CPU and sources of interrupts present per-
formance issues for you to consider when you are developing your code.
7.5.1
General Performance
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Overhead. Overhead for all CPU interrupts is seven cycles for the ’C62x
and nine cycles for the ’C67x. You can see this in Figure 7–12 and
Figure 7–13, where no new instructions are entering the E1 pipeline
phase during CPU cycles 6 through 12 for the ’C62x and CPU cycles 6
through 14 for the ’C67x.
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Latency. Interrupt latency is 11 cycles for the ’C62x and 13 cycles for the
’C67x (21 cycles for RESET). In Figure 7–13, although the interrupt is
active in cycle 2, execution of interrupt service code does not begin until
cycle 13 for the ’C62x and cycle 15 for the ’C67x.
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Frequency. The logic clears the nonreset interrupt (IFm) on cycle 8, with
any incoming interrupt having highest priority. Thus, an interrupt can be
recognized every second cycle. Also, because a low-to-high transition is
necessary, an interrupt can occur only every second cycle. However, the
frequency of interrupt processing depends on the time required for inter-
rupt service and whether you reenable interrupts during processing,
thereby allowing nested interrupts. Effectively, only two occurrences of a
specific interrupt can be recognized in two cycles.
7.5.2
Pipeline Interaction
Because the serial or parallel encoding of fetch packets does not affect the DC
and subsequent phases of the pipeline, no conflicts between code parallelism
and interrupts exist. There are three operations or conditions that can affect,
or are affected by, interrupts:
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Branches. Nonreset interrupts are delayed if any execute packets n
through n + 4 in Figure 7–12 or Figure 7–13 contain a branch or are in the
delay slots of a branch.
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Memory stalls. Memory stalls delay interrupt processing, because they
inherently extend CPU cycles.
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Multicycle NOPs. Multicycle NOPs (including IDLE) operate like other
instructions when interrupted, except when an interrupt causes annul-
ment of any but the first cycle of a multicycle NOP. In that case, the address
of the
next execute packet in the pipeline is saved in the NRP or the IRP.
This prevents returning to an IDLE instruction or a multicycle NOP that
was interrupted.
