Performance Considerations
6-59
TMS320C67x Pipeline
Table 6–34. Loads in Pipeline From Example 6–2
i
i + 1
i + 2
i + 3
i + 4
i + 5
LDW .D1
Bank 0
E1
E2
E3
–
E4
E5
LDW .D2
Bank 0
E1
E2
–
E3
E4
E5
For devices that have more than one memory space (see Figure 6–32), an
access to bank 0 in one space does not interfere with an access to bank 0 in
another memory space, and no pipeline stall occurs.
The internal memory of the ’C67x family varies from device to device. See the
TMS320C62x/C67x Peripherals Reference Guide to determine the memory
spaces in your particular device.
Figure 6–32. 8-Bank Interleaved Memory With Two Memory Spaces
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
+1
M
Bank 0
16N
16N
16N
16N
16N
16N
16N
16N
16N
16N
16N
16N
16N
16N
16N
16N
0
1
16
17
Bank 0
2
3
18
19
Bank 1
4
5
20
21
Bank 2
6
7
22
23
Bank 3
8
9
24
25
Bank 4
10
11
26
27
Bank 5
12
13
28
29
Bank 6
14
15
30
31
Bank 7
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
1
2
3
4
5
6
7
8
9
0
1
1
1
12
13
14
15
16
16M
16M
16M
16M
16M
16M
16M
16M
16M
16M
16M
16M
16M
16M
16M
+
+
+
+
+
+
+
+
+
+
+
+
+
+
2
3
4
5
6
7
8
9
0
1
1
1
12
13
14
15
Memory space 1
Memory space 0
