Pipeline Execution of Instruction Types
5-13
TMS320C62x Pipeline
Figure 5–11 shows the operations occurring in the pipeline for a multiply. In the
E1 phase, the operands are read and the multiply begins. In the E2 phase, the
multiply finishes, and the result is written to the destination register. Multiply
instructions have one delay slot.
Figure 5–11.Multiply Execution Block Diagram
(data)
Operands
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Register file
Write results
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
Functional
unit
.M
E1
E2
5.2.3
Store Instructions
Store instructions require phases E1 through E3 to complete their operations.
Figure 5–12 shows the pipeline phases the store instructions use.
Figure 5–12. Store Instruction Phases
PG
PS
PW
PR
DP
DC
E1
E2
E3
Address
modification
Figure 5–13 shows the operations occurring in the pipeline phases for a store.
In the E1 phase, the address of the data to be stored is computed. In the E2
phase, the data and destination addresses are sent to data memory. In the E3
phase, a memory write is performed. The address modification is performed
in the E1 stage of the pipeline. Even though stores finish their execution in the
E3 phase of the pipeline, they have no delay slots.
