Individual Interrupt Control
7-16
7.3.3
Returning From Interrupt Servicing
After RESET goes high, the control registers are brought to a known value and
program execution begins at address 0h. After nonmaskable and maskable
interrupt servicing, use a branch to the corresponding return pointer register
to continue the previous program execution.
7.3.3.1
CPU State After RESET
After RESET, the control registers and bits will contain the corresponding val-
ues:
-
AMR, ISR, ICR, IFR, and ISTP = 0h
-
IER = 1h
-
IRP and NRP = undefined
-
Bits 15–0 of the CSR = 100h in little-endian mode
= 000h in big-endian mode
7.3.3.2
Returning From Nonmaskable Interrupts (NMI Return Pointer Register–NRP)
The NMI return pointer register (NRP) contains the return pointer that directs
the CPU to the proper location to continue program execution after NMI
processing. A branch using the address in the NRP (B NRP) in your interrupt
service routine returns to the program flow when NMI servicing is complete.
Example 7–8 shows how to return from an NMI.
Example 7–8. Code to Return From NMI
B
NRP
; return, sets NMIE
NOP
5
; delay slots
The NRP contains the 32-bit address of the first execute packet in the program
flow that was not executed because of a nonmaskable interrupt. Although you
can write a value to this register, any subsequent interrupt processing may
overwrite that value. Figure 7–10 shows the NRP register.
Figure 7–10. NMI Return Pointer (NRP)
31
16
NRP
R, W, +x
15
0
NRP
R, W, +x
Legend: R = Readable by the MVC instruction
W = Writeable by the MVC instruction
+x = value undefined after reset
