Interrupt Detection and Processing
7-21
Interrupts
7.4.3
Actions Taken During Nonreset Interrupt Processing
During CPU cycles 6–12 of Figure 7–12 and cycles 6–14 of Figure 7–13, the
following interrupt processing actions occur:
-
Processing of subsequent nonreset interrupts is disabled.
-
For all interrupts except NMI, PGIE is set to the value of GIE and then GIE
is cleared.
-
For NMI, NMIE is cleared.
-
The next execute packets (from n + 5 on) are annulled.
If an execute pack-
et is annulled during a particular pipeline stage, it does not modify any CPU
state. Annulling also forces an instruction to be annulled in future pipeline
stages.
-
The address of the first annulled execute packet (n+5) is loaded in to the
NRP (in the case of NMI) or IRP (for all other interrupts).
-
A branch to the address held in ISTP (the pointer to the ISFP for INTm)
is forced into the E1 phase of the pipeline during cycle 7 for the ’C62x and
cycle 9 for the ’C67x.
-
During cycle 7, IACK is asserted and the proper INUMx signals are
asserted to indicate which interrupt is being processed. The timings for
these signals in Figure 7–12 and Figure 7–13 represent only the signals’
characteristics inside the CPU. The external signals may be delayed and
be longer in duration to handle external devices. Check the data sheet for
your specific device for particular timing values.
-
IFm is cleared during cycle 8.
