Store to Memory With a Register Offset or 5-Bit Unsigned Constant Offset
STB/STH/STW
3-123
TMS320C62x/C67x Fixed-Point Instruction Set
Table 3–17. Data Types Supported by Stores
Mnemonic
ld/st
Field
Store Data Type
SIze
Left Shift of Offset
STB
0 1 1 Store byte
8
0 bits
STH
1 0 1 Store halfword
16
1 bit
STW
1 1 1 Store word
32
2 bits
Table 3–18. Address Generator Options
Mode Field
Syntax
Modification Performed
0
1
0
1
*+R[
offsetR]
Positive offset
0
1
0
0
*–R[
offsetR]
Negative offset
1
1
0
1
*+ +R[
offsetR]
Preincrement
1
1
0
0
*– –R[
offsetR]
Predecrement
1
1
1
1
*R+ +[
offsetR]
Postincrement
1
1
1
0
*R– –[
offsetR]
Postdecrement
0
0
0
1
*+R[
ucst5]
Positive offset
0
0
0
0
*–R[
ucst5]
Negative offset
1
0
0
1
*+ +R[
ucst5]
Preincrement
1
0
0
0
*– –R[
ucst5]
Predecrement
1
0
1
1
*R+ +[
ucst5]
Postincrement
1
0
1
0
*R– –[
ucst5]
Postdecrement
Increments and decrements default to 1 and offsets default to zero when no
bracketed register or constant is specified. Stores that do no modification to
the
baseR can use the syntax *R. Square brackets, [ ], indicate that the ucst5
offset is left-shifted by 2, 1, or 0 for word, halfword, and byte loads, respectively.
Parentheses, ( ), can be used to set a nonscaled, constant offset. For example,
STW (.unit) *+
baseR(12) dst represents an offset of 12 bytes whereas STW
(.unit) *+
baseR[12] dst represents an offset of 12 words, or 48 bytes. You must
type either brackets or parentheses around the specified offset if you use the
optional offset parameter.
Word and halfword addresses must be aligned on word (two LSBs are 0) and
halfword (LSB is 0) boundaries, respectively.
Execution
if (cond)
src
→
mem
else
nop
