TMS320C62x/C67x Control Register File
2-11
CPU Data Paths and Control
2.6.2
Control Status Register (CSR)
The CSR, shown in Figure 2–5, contains control and status bits. The functions
of the fields in the CSR are shown in Table 2–6. For the EN, PWRD, PCC, and
DCC fields, see your data sheet to see if your device supports the options that
these fields control and see the
TMS320C6201/C6701 Peripherals Reference
Guide for more information on these options.
Figure 2–5. Control Status Register (CSR)
31
24
CPU ID
16
23
Revision ID
R
15
PWRD
SAT
EN
PCC
DCC
10
9
8
7
5
4
2
1
0
PGIE
GIE
R, W, +0
R, +x
R, W, +0
R, C, +0
Legend: R
Readable by the MVC instruction
W
Writeable by the MVC instruction
+x
Value undefined after reset
+0
Value is zero after reset
C
Clearable using the MVC instruction
Table 2–6. Control Status Register Field Descriptions
Bit Position
Width
Field Name
Function
31-24
8
CPU ID
CPU ID; defines which CPU.
CPU ID = 00b: indicates ’C62x, CPU ID= 10b: indicates ’C67x
23-16
8
Revision ID
Revision ID; defines silicon revision of the CPU
15-10
6
PWRD
Control power-down modes; the values are always read as zero.
†
9
1
SAT
The saturate bit, set when any unit performs a saturate, can be
cleared only by the MVC instruction and can be set only by a func-
tional unit. The set by a functional unit has priority over a clear (by
the MVC instruction) if they occur on the same cycle. The saturate
bit is set one full cycle (one delay slot) after a saturate occurs. This
bit will not be modified by a conditional instruction whose condition
is false.
8
1
EN
Endian bit: 1 = little endian, 0 = big endian
†
7-5
3
PCC
Program cache control mode
†
4-2
3
DCC
Data cache control mode
†
1
1
PGIE
Previous GIE (global interrupt enable); saves GIE when an inter-
rupt is taken
0
1
GIE
Global interrupt enable; enables (1) or disables (0) all interrupts
except the reset interrupt and NMI (nonmaskable interrupt)
† See the TMS320C6201/C6701 Peripherals Reference Guide for more information.
