Pipeline Execution of Instruction Types
6-16
The execution of instructions can be defined in terms of delay slots. A delay
slot is a CPU cycle that occurs after the first execution phase (E1) of an instruc-
tion. Results from instructions with delay slots are not available until the end
of the last delay slot. For example, a multiply instruction has one delay slot,
which means that one CPU cycle elapses before the results of the multiply are
available for use by a subsequent instruction. However, results are available
from other instructions finishing execution during the same CPU cycle in which
the multiply is in a delay slot.
If an instruction has a multicycle functional unit latency, it locks the functional
unit for the necessary number of cycles. Any new instruction dispatched to that
functional unit during this locking period causes undefined results. If an in-
struction with a multicycle functional unit latency has a condition that is evalu-
ated as false during E1, it still locks the functional unit for subsequent cycles.
An instruction of the following types scheduled on cycle i has the following
constraints:
DP compare
No other instruction can use the functional unit on cycles
i and i + 1.
ADDDP/SUBDP
No other instruction can use the functional unit on cycles
i and i + 1.
MPYI
No other instruction can use the functional unit on cycles
i, i + 1, i + 2, and i + 3.
MPYID
No other instruction can use the functional unit on cycles
i, i + 1, i + 2, and i + 3.
MPYDP
No other instruction can use the functional unit on cycles
i, i + 1, i + 2, and i + 3.
If a cross path is used to read a source using an instruction with multicycle
functional unit latency, ensure that no other instructions executing on the same
side use the cross path.
