Pipeline Execution of Instruction Types
5-16
In the following code, pointer results are written to the A4 register in the first
execute phase of the pipeline and data is written to the A3 register in the fifth
execute phase.
LDW .D1 *A4++,A3
Because a store takes three execute phases to write a value to memory and
a load takes three execute phases to read from memory, a load following a
store accesses the value placed in memory by that store in the cycle after the
store is completed. This is why the store is considered to have zero delay slots.
5.2.5
Branch Instructions
Although branch takes one execute phase, there are five delay slots between
the execution of the branch and execution of the target code. Figure 5–16
shows the pipeline phases used by the branch instruction and branch target
code. The delay slots are shaded.
Figure 5–16. Branch Instruction Phases
Branch
target
PG
PS
PW
PR
DP
DC
E1
5 delay slots
PG
PS
PW
PR
DP
DC
E1
