Interrupt Detection and Processing
7-18
7.4
Interrupt Detection and Processing
When an interrupt occurs, it sets a flag in the IFR. Depending on certain condi-
tions, the interrupt may or may not be processed. This section discusses the
mechanics of setting the flag bit, the conditions for processing an interrupt, and
the order of operation for detecting and processing an interrupt. The similari-
ties and differences between reset and nonreset interrupts are also discussed.
7.4.1
Setting the Nonreset Interrupt Flag
Figure 7–12 and Figure 7–13 show the processing of a nonreset interrupt
(INTm) for the ’C62x and ’C67x, respectively. The flag (IFm) for INTm in the
IFR is set following the low-to-high transition of the INTm signal on the CPU
boundary. This transition is detected on a clock-cycle by clock-cycle basis and
is not affected by memory stalls that might extend a CPU cycle. Once there is
a low-to-high transition on an external interrupt pin (cycle 1), it takes two clock
cycles for the signal to reach the CPU boundary (cycle 3). When the interrupt
signal enters the CPU, it is has been detected (cycle 4). Two clock cycles after
detection, the interrupt’s corresponding flag bit in the IFR is set (cycle 6).
In Figure 7–12 and Figure 7–13, IFm is set during CPU cycle 6. You could at-
tempt to clear bit IFm by using an MVC instruction to write a 1 to bit m of the
ICR in execute packet n + 3 (during CPU cycle 4). However, in this case, the
automated write by the interrupt detection logic takes precedence and IFm re-
mains set.
Figure 7–12 and Figure 7–13 assume INTm is the highest priority pending in-
terrupt and is enabled by GIE and NMIE as necessary. If it is not the highest
priority pending interrupt, IFm remains set until either you clear it by writing a1
to bit m of the ICR, or the processing of INTm occurs.
7.4.2
Conditions for Processing a Nonreset Interrupt
In clock cycle 4 of Figure 7–12 and Figure 7–13, a nonreset interrupt in need
of processing is detected. For this interrupt to be processed, the following
conditions must be valid on the same clock cycle and are evaluated every
clock cycle:
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IFm is set during CPU cycle 6. (This determination is made in CPU cycle
4 by the interrupt logic.)
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There is not a higher priority IFm bit set in the IFR.
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The corresponding bit in the IER is set (IEm = 1).
