Globally Enabling and Disabling Interrupts
7-11
Interrupts
7.2
Globally Enabling and Disabling Interrupts
(Control Status Register–CSR)
The control status register (CSR) contains two fields that control interrupts:
GIE and PGIE, as shown in Figure 7–5 and Table 7–4. The other fields of the
registers serve other purposes and are discussed in section 2.6.2 on page
2-11.
Figure 7–5. Control Status Register (CSR)
31
24
CPU ID
16
23
Revision ID
R
15
PWRD
SAT
EN
PCC
DCC
10
9
8
7
5
4
2
1
0
PGIE
GIE
R, W, +0
R, +x
R, W, +0
R, C, +0
Legend: R
Readable by the MVC instruction
W
Writeable by the MVC instruction
+x
Value undefined after reset
+0
Value is zero after reset
C
Clearable using the MVC instruction
Table 7–4. Control Status Register (CSR) Interrupt Control Field Descriptions
Bit
Field
Name
Description
0
GIE
Global interrupt enable; globally enables or disables all
maskable interrupts.
GIE = 1: maskable interrupts globally enabled
GIE = 0: maskable interrupts globally disabled
1
PGIE
Previous GIE; saves the value of GIE when an interrupt is
taken. This value is used on return from an interrupt.
The global interrupt enable (GIE) allows you to enable or disable all maskable
interrupts by controlling the value of a single bit. GIE is bit 0 of the control status
register (CSR).
-
GIE = 1 enables the maskable interrupts so that they are processed.
-
GIE = 0 disables the maskable interrupts so that they are not processed.
Bit 1 of the CSR is PGIE and contains the previous value of GIE. During pro-
cessing of a maskable interrupt, PGIE is loaded with GIE and GIE is cleared.
GIE is cleared during a maskable interrupt to keep another maskable interrupt
from occurring before the device state has been saved. Upon return from an
interrupt, by way of the B IRP instruction, the PGIE value is copied back to GIE
and remains unchanged. The purpose of PGIE is to allow proper clearing of
GIE when an interrupt has already been detected for processing.
Globally Enabling and Disabling Interrupts (Control Status Register–CSR)
