TMS320C62x/C67x Architecture
1-8
1.4.1
Central Processing Unit (CPU)
The ’C62x/C67x CPU, shaded in Figure 1–1, is common to all the ’C62x/C67x
devices. The CPU contains:
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Program fetch unit
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Instruction dispatch unit
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Instruction decode unit
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Two data paths, each with four functional units
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32 32-bit registers
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Control registers
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Control logic
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Test, emulation, and interrupt logic
The program fetch, instruction dispatch, and instruction decode units can
deliver up to eight 32-bit instructions to the functional units every CPU clock
cycle. The processing of instructions occurs in each of the two data paths (A
and B), each of which contains four functional units (.L, .S, .M, and .D) and 16
32-bit general-purpose registers. The data paths are described in more detail
in Chapter 2,
CPU Data Paths and Control. A control register file provides the
means to configure and control various processor operations. To understand
how instructions are fetched, dispatched, decoded, and executed in the data
path, see Chapter 5,
TMS320C62x Pipeline, and Chapter 6, TMS320C67x
Pipeline.
1.4.2
Internal Memory
The ’C62x/C67x have a 32-bit, byte-addressable address space. Internal (on-
chip) memory is organized in separate data and program spaces. When off-
chip memory is used, these spaces are unified on most devices to a single
memory space via the external memory interface (EMIF).
The ’C62x/C67x have two 32-bit internal ports to access internal data memory.
The ’C62x/C67x have a single internal port to access internal program
memory, with an instruction-fetch width of 256 bits.
