Models 707B and 708B Switching Matrix Reference Manual
Appendix C: Status model
707B-901-01 Rev. B / January 2015
C-7
As shown above, there are five register sets associated with System Event Status. These registers
summarize system status for various nodes connected to the TSP-Link. Note that all nodes on the
TSP-Link share a copy of the system summary registers once the TSP-Link has been initialized. This
feature allows all nodes to access the status models of other nodes, including SRQ.
In a TSP-Link system, the status model can be configured such that a status event in any node in the
system can set the RQS (Request for Service) bit of the Master Node Status Byte. See
(on page C-21) for details on using the status model in a TSP-Link system.
Attributes are summarized in
(on page 7-192),
(on page 7-194),
For example, any of the following commands will set the EXT enable bit:
status.system.enable = status.system.EXT
status.system.enable = status.system.EXTENSION_BIT
status.system.enable = 1
When reading a register, a numeric value is returned. The binary equivalent of this value indicates
which bits in the register are set. For details, see
(on page C-15). For example, the
following command will read the system enable register:
print(status.system.enable)
The bits used in the system register sets are described as follows:
•
Bit B0, Extension Bit (EXT):
Set bit indicates that an extension bit from another system status
register is set.
•
Bits B1-B14* NODEN:
Indicates a bit on TSP-Link node n has been set (
N
= 1 to 64).
•
Bits B15:
Not used.
*
status.system5
does not use bits B9 through B15.
Refer to the following table for available
N
values:
Command
N value
status.system.*
1 to 14
status.system2.*
15 to 28
status.system3.*
29 to 42
status.system4.*
43 to 56
status.system5.*
57 to 64
Error available bit (Error or Event queue)
The summary bit of the Error or Event queue provides enabled summary information to Bit B2 (EAV)
of the status byte.
The Error Available Bit (EAV) is set when a message defining an error (or status) is placed in the
Error or Event queue. The Error or Event queue is one of the two Switching Matrix queues associated
with the status model. The other queue sets the Message available bit (Output queue)). Both queues
are first-in, first-out (FIFO) queues. The Error queue holds error and status messages. The status
model shows how these queues are structured with regard to the other registers.