Models 707B and 708B Switching Matrix Reference Manual
Appendix C: Status model
707B-901-01 Rev. B / January 2015
C-9
As shown above, there is only one register set associated with the questionable status. Attributes are
summarized in
(on page 7-181). Keep in mind that bits can also be set by using
numeric parameter values. For details, see
Programming enable and transition registers
(on page C-
For example, any of the following statements will set the thermal aspect enable bit of a card in slot 1:
status.questionable.enable = status.questionable.S1THR
status.questionable.enable = status.questionable.SLOT1_THERMAL
status.questionable.enable = 512
The following command will request the questionable enable register value in numeric form:
print(status.questionable.enable)
The bits used in this register set are described as follows:
•
SxTHR:
Set bit indicates the thermal aspect of the card in slot x is in question, where x = 1 to 6.
Message available bit (Output queue)
The summary bit of the output queue provides enabled summary information to Bit B4 (MAV) of the
status byte.
The Message Available Bit (MAV) is set when the Output queue holds data that pertains to the
normal operation of the instrument. The Output queue is one of the two Switching Matrix queues
associated with the status model. The other queue sets the
Error Available Bit (Error or Event queue)
(on page C-7). Both queues are first-in, first-out (FIFO) queues. The
(on page C-4) shows how these queues are structured with regard to the other registers.
As an example, when a print command is sent, the response message is placed in the Output queue.
When data is placed in the Output queue, the Message Available (MAV) bit in the Status Byte
Register sets. A response message is cleared from the Output queue when it is read. The Output
queue is considered cleared when it is empty. An empty Output queue clears the MAV bit in the
Status Byte Register.
A message is read from the Output queue by addressing the Switching Matrix to talk.
Event summary bit (ESB register)
The summary bit of the Standard event register provides enabled summary information to Bit B5
(OSB) of the status byte.
Figure 108: Event summary bit (Standard event register)