Supero SUPER 370DDE, User Manual

Page: 61 / 171

Chapter 4: Award BIOS
4-9
BIOS
This section documents the functionality that the AwardBIOS provides the
user in configuring the system based upon the special features offered by
the VIA Apollo 266 chipset. The VIA Apollo 266 chipset manages the
operations of major components of the board, such as the bus speed of the
CPU, the access to the memory and the communication between the PCI slots
and the CPU. Normally, the default settings for the Advanced Chipset
Features listed in the section are pre-configured by the manufacturer for the
optimal performance of the system. It is not recommended that the user alter
the default settings. This section is provided as an emergency measure for
the user to restore the functions of the system when the critical data stored
in the BIOS is lost.
When the item in "Advanced Chipset Features" is highlighted, hit the <Enter>
key to activate the screen below:
[Host & AGP Bridge Control]
This section documents the AwardBIOS management of the bus links
between host and bridge devices.
[Memory Parity / ECC Check]
"Enabled" adds a parity check to the boot-up memory tests. Select "Enabled"
only if the system DRAM contains parity.
[System BIOS Cacheable]
If enabled, the system BIOS information stored in the BIOS ROM (Read Only
Memory) chip will be written and temporarily stored in the "cacheable"
section of the memory, so the CPU has faster access to the information.
The settings are: "Enabled" or "Disabled." The default setting is "Enabled."